SEGGER Assembler User Guide & Reference Manual

An assembler for Arm microcontrollers.

About the assembler

Introduction

This section presents an overview of the SEGGER Assembler and its capabilities.

What is the SEGGER Assembler?

The SEGGER Assembler is a fast assembler that processes Cortex-M assembly language source files. It is designed to be very flexible, yet simple to use.

The assembler accepts GNU, Arm, and IAR syntax source files and will assemble them to Arm ELF object files that can be linked by a standard Cortex-M linker.

Assembler features

The SEGGER Assembler has the following features:

• Highly efficient and very fast to assemble.
• Supports GNU, Arm, and IAR syntax.

Command-line options

Command line option naming is generally compatible with the following toolsets:

• GNU assembler as
• Arm assembler armasm
• IAR assembler iasmarm

Input file options

--auto-import

Summary

Automatically import symbols.

Syntax

--auto-import

Description

This option instructs the assembler to automatically define as symbol as an external (imported) symbol if it is used and has not been declared with a different storage class.

See also

--no-auto-import

--no-auto-import

Summary

Do not automatically import symbols.

Syntax

--no-auto-import

Description

This option instructs the assembler not to automatically define as symbol as an external (imported) symbol and to require that all symbols are declared as local or external before their first use.

See also

--auto-import

--define

Summary

Define symbol.

Syntax

--define symbol=value
-Dsymbol=value

Description

This option defines the symbol symbol to the numeric value value.

--dependency-file

Summary

Write dependencies to file.

Syntax

--dependency-file filename
--MD filename

Description

This option instructs the assembler to write the list of dependencies (included source files and included binary files) to the fle filename.

--include

Summary

Add include directory.

Syntax

--include path
-Ipath

Description

This option adds the path path to the end of the list of directories to search for included source files and included binary files.

--input-syntax

Summary

Set source file syntax.

Syntax

--input-syntax=name
-fsyntax=name

Description

This option selects the source file syntax. The syntaxes accepted by the assembler are:

• arm — Format is compatible with ARM Limited’s armasm assembler.
• iar — Format is compatible with IAR’s iasmarm assembler.
• gnu — Format is compatible with The Free Software Foundation’s gas assembler.

There is one additional syntax identifier:

• auto — Source format is automatically derived from the input file.

The default is auto syntax where the assembler automatically determines the appropriate source file syntax using heuristics.

--via

Synopsis

Read additional options and input files from file.

Syntax

--via filename
--via=filename
-f filename
@filename

Description

This option reads the file filename for additional options and input files. Options are separated by spaces or newlines, and file names which contain special characters, such as spaces, must be enclosed in double quotation marks.

Notes

This option can only be provided on the command line and cannot appear in an indirect file.

Output file options

--keep-empty-sections

Summary

Keep empty sections in object file.

Syntax

--keep-empty-sections

Description

This option instructs the assembler to emit empty sections that have been created during assembly. An empty section is a section that is created using a section directive but has no instructions or data allocated to it.

The default is to eliminate empty sections.

See also

--no-keep-empty-sections

--no-keep-empty-sections

Summary

Eliminate empty sections from object file.

Syntax

--no-keep-empty-sections

Description

This option instructs the assembler to eliminate empty sections that have been created during assembly. An empty section is a section that is created using a section directive but has no instructions or data allocated to it.

The default is to eliminate empty sections.

See also

--keep-empty-sections

--keep-local-symbols

Summary

Keep local symbol definitions in object file.

Syntax

--keep-local-symbols

Description

This option instructs the assembler to include local symbol definitions created during assembly in the object file’s symbol table. Local symbols can be either an equate or a local label definition that is not exported as a global symbol.

The default is eliminate local symbols.

Note

Local symbols that start “.L” are never emitted to the object even with --keep-local-symbols in effect.

See also

--no-keep-local-symbols

--no-keep-local-symbols

Summary

Do not keep local symbol definitions in object file.

Syntax

--no-keep-local-symbols

Description

This option instructs the assembler to exclude local symbol definitions created during assembly from the object file’s symbol table. Local symbols can be either an equate or a local label definition that is not exported as a global symbol.

See also

--keep-local-symbols

--mapping-symbols

Summary

Include mapping symbols.

Syntax

--mapping-symbols

Description

This option includes mapping symbols in the Arm ELF file.

See also

--no-mapping-symbols

--no-mapping-symbols

Summary

Do not generate mapping symbols.

Syntax

--no-mapping-symbols

Description

This option produces an Arm ELF file that contains no code and data mapping symbols.

See also

--mapping-symbols

--output

Summary

Set output file name.

Syntax

--output filename
-o filename

--output=filename
-o=filename

Description

This option sets the Arm ELF output filename, typically with extension “o”.

--symbols

Summary

Include symbol table.

Syntax

--symbols

Description

This option includes the symbol table in the Arm ELF file. This does not automatically enable mapping symbol inclusion.

See also

--no-symbols

--no-symbols

Summary

Discard symbol table.

Syntax

--no-symbols

Description

This option eliminates all symbols from the Arm ELF file that are not required which includes the mapping symbols.

See also

--symbols

--pad-sections

Summary

Pad sections to alignment boundary.

Syntax

--pad-sections

Description

This option instructs the assembler to emit additional data to a section such that its size is a multiple of its alignment. Padding a section to a multiple of its alignment may waste space that a linker could otherwise utilize for section packing.

The default is not to pad sections.

See also

--no-pad-sections

--no-pad-sections

Summary

Do not pad sections to alignment boundary.

Syntax

--no-pad-sections

Description

This option instructs the assembler not to emit additional data to a section such that its size is a multiple of its alignment. Padding a section to a multiple of its alignment may waste space that a linker could otherwise utilize for section packing.

The default is not to pad sections.

See also

--pad-sections

Target selection options

--cpu=name

Summary

Set target core or architecture.

Syntax

--cpu=name
-cpu=name
-mcpu=name

Description

This option selects the target processor for the application and controls the construction of appropriate veneers when required.

The core names accepted are:

• cortex-m0, cortex-m0plus, cortex-m0+, cortex-m1, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33
• cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75
• cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, cortex-r52

The architecture names accepted are:

• 4t, 5t, 5te
• 6, 6j, 6k, 6kz, 6t2, 6z, 6zk, 6-m, 6s-m
• 7, 7ve, 7-a, 7-r, 7-m, 7e-m
• 8-a, 8.1-a, 8.2-a, 8.3-a, 8.4-a, 8-r, 8-m.base, 8-m.main

The default is --cpu=cortex-m0.

-marm

Summary

Select Arm instruction set.

Syntax

-marm

Description

This option sets the default assembler instruction set to Arm (A32). The default instruction set is the instruction set if the source file does not select a specific instruction set using assembler source directives.

See also

-mthumb

-mbig-endian

Summary

Select big-endian byte order.

Syntax

-mbig-endian
-EB

Description

This option selects big-endian byte ordering for data and instructions.

The default is little-endian byte ordering.

See also

-mlittle-endian

-mlittle-endian

Summary

Select little-endian byte order.

Syntax

-mlittle-endian
-EL

Description

This option selects little-endian byte ordering for data and instructions.

The default is little-endian byte ordering.

See also

-mbig-endian

-mthumb

Summary

Select Thumb instruction set.

Syntax

-mthumb

Description

This option sets the default assembler instruction set to Thumb (T32). The default instruction set is the instruction set if the source file does not select a specific instruction set using assembler source directives.

See also

-marm

List file options

--list-diagnostics

Summary

Print diagnostics to listing.

Syntax

--list-diagnostics

Description

This option instructs the assembler to print all diagnostics at the end of the listing.

See also

--no-list-diagnostics

--no-list-diagnostics

Summary

Do not print diagnostics to listing.

Syntax

--no-list-diagnostics

Description

This option instructs the assembler not to print diagnostics at the end of the listing.

See also

--list-diagnostics

--list-file

Summary

Generate an assembler listing file.

Syntax

--list-file filename
--list-file=filename
-Lfilename

Description

Generates an assembler listing to the given filename.

--list-form-feed

Summary

Issue form feed between pages.

Syntax

--list-form-feed

Description

This option instructs the assembler to write a form feed between listing pages.

See also

--list-page-length, --no-list-form-feed

--no-list-form-feed

Summary

Do not issue form feed between pages.

Syntax

--no-list-form-feed

Description

This option ibhibits the assembler writing a form feed between listing pages.

See also

--list-form-feed

--list-html

Summary

Format listing as an HTML document.

Syntax

--list-html

Description

This option instructs the assembler to format the assembler listing as an HTML document. In this mode, listing pagination controls are ignored.

See also

--list-text

--list-page-length

Summary

Set number of lines per page.

Syntax

--list-page-length=value

Description

This option sets the number of lines per page to value. If value is zero, which is the default, the listing is not divided into pages.

See also

--list-form-feed

--list-symbols

Summary

Print symbol table to listing.

Syntax

--list-symbols

Description

This option instructs the assembler to print a symbol table at the end of the listing.

See also

--no-list-symbols

--no-list-symbols

Summary

Do not print symbol table to listing.

Syntax

--no-list-symbols

Description

This option instructs the assembler not to print a symbol table at the end of the listing.

See also

--list-symbols

--list-text

Summary

Format listing as a text document.

Syntax

--list-text

Description

This option instructs the assembler to format the assembler listing as an HTML document. In this mode, listing pagination controls are effective.

This is the default.

See also

--list-html

Control options

--remarks

Summary

Issue remarks.

Syntax

--remarks

Description

This option instructs the assembler to issue remarks for potential issues during assembly. This is the default.

See also

--no-remarks, --remarks-are-warnings, --remarks-are-errors

--remarks-are-errors

Summary

Elevate remarks to errors.

Syntax

--remarks-are-errors

Description

This option elevates all remark diagnostics issued by the assembler to errors.

See also

--no-remarks, --remarks, , --remarks-are-warnings

--remarks-are-warnings

Summary

Elevate remarks to warnings.

Syntax

--remarks-are-warnings
--remarks_are_warnings

Description

This option elevates all remark diagnostics issued by the assembler to warnings.

See also

--no-remarks, --remarks, , --remarks-are-errors

--no-remarks

Summary

Suppress remarks.

Syntax

--no-remarks

Description

This option disables all remark diagnostics issued by the assembler. Although remarks are suppressed, the total number of remarks that are suppressed by the assembler is shown at the end of linking:

C:> segger-as --via=app.ind
Copyright (c) 2017-2018 SEGGER Microcontroller GmbH    www.segger.com
SEGGER Assembler 2.10 compiled Apr 11 2018 10:50:34

Assembly complete: 0 errors, 0 warnings, 2 remarks suppressed

C:> _

See also

--remarks-are-warnings, --remarks-are-errors

--silent

Summary

Do not show output.

Syntax

--silent
-q

Description

This option inhibits all assembler status messages; only diagnostic messages are shown.

See also

--verbose

--verbose

Summary

Increase verbosity.

Syntax

--verbose
-v

Description

This option increase the verbosity of the assembler by one level.

See also

--silent

--warnings

Summary

Issue warnings.

Syntax

--warnings

Description

This option instructs the assembler to issue warnings for dubious use or inputs. This is the default.

See also

--no-warnings, --warnings-are-errors

--warnings-are-errors

Summary

Elevate warnings to errors.

Syntax

--warnings-are-errors
--fatal-warnings

Description

This option elevates all warning diagnostics issued by the assembler to errors.

See also

--no-warnings, --warnings

--no-warnings

Summary

Suppress warnings.

Syntax

--no-warnings

Description

This option disables all warning diagnostics issued by the assembler. Although warnings are suppressed, the total number of warnings that are suppressed by the assembler is shown at the end of linking:

C:> segger-as --via=app.ind
SEGGER Macro Assembler V2.10 compiled Jul  9 2020 14:30:42
Copyright (c) 2018-2020 SEGGER Microcontroller GmbH    www.segger.com

Assembly complete: 0 errors, 1 warnings suppressed, 0 remarks

C:> _

See also

--warnings, --warnings-are-errors

Expressions

GNU	IAR	ARM
(), prefix +, -, !, ~	(), prefix +, -, !, ~, LOW, HIGH, BYTE1, BYTE2, BYTE3, BYTE4, LWRD, HWRD, DATE, SFB, SFE, SIZEOF	(), prefix +, -, :NOT:, :LNOT:
*, /, %, <<, >>	*, /, %	*, /, %, :MOD:
|, &, ^, !	+, -	<<, >>, :SHL:, :SHR:, :ROL:, :ROR:
+, -, =, <>, ≠, <, >, ≤, ≥	<<, >>	+, -, &, ^, :AND:, :OR:, :EOR:
&&, ||	&&, &	=, <>, ≠, /=, <, >, ≤, ≥
	||, |, ^, XOR	&&, ||, :LAND:, :LOR:, :LEOR:
	=, =, <>, ≠, <, >, ≤, ≥, UGT, ULT

GNU syntax

Source file directives

.INCBIN

Include binary file.

Syntax

.INCBIN “filename”

Description

Searches for the binary file filename using include paths. Inserts the binary file into the current section as data with alignment 1.

Mode directives

.ARM

Select Arm instruction set.

Syntax

.ARM

Description

Selects the Arm instruction set for following instructions.

See also

.THUMB

.CODE

Select instruction set.

Syntax

.CODE 16
.CODE 32

Description

Selects the Arm or Thumb instruction set according to operand.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_CODE.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .TEXT
   2                                 
   3                                    .CODE 16
   4                                 
   5             00000000 0120           MOVS R0, #1
   6             00000002 4018           ADDS R0, R0, R1
   7                                 
   8                                    .CODE 32
   9                                 
  10             00000004 0100B0E3       MOVS R0, #1
  11             00000008 010090E0       ADDS R0, R0, R1
  12                                 
  13                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.ARM, .THUMB

.THUMB

Select Thumb instruction set.

Syntax

.THUMB

Description

Selects the Thumb instruction set for following instructions.

See also

.ARM

Section directives

.DATA

Switch to data section

Syntax

.DATA

Description

Switches to the .data section.

.BSS

Switch to bss section

Syntax

.BSS

Description

Switches to the .bss section.

.TEXT

Switch to text section

Syntax

.TEXT

Description

Switches to the .text section.

.RODATA

Switch to data section

Syntax

.RODATA

Description

Switches to the .rodata section.

Symbol directives

.GLOBL, .GLOBAL, .EXTERN

Set external symbol binding.

Syntax

.GLOBL name, name…
.GLOBAL name, name…
.EXTERN name, name…

Description

Defines all symbols in the symbol list to have global binding so that they are externally visible.

.LOCAL

Set local symbol binding.

Syntax

.LOCAL name, name…

Description

Defines all symbols in the symbol list to have local binding so that they are not externally visible.

.WEAK

Set weak symbol binding.

Syntax

.WEAK name, name…

Description

Defines all symbols in the symbol list to have weak binding so that they can be overridden when linked.

.HIDDEN

Set symbol visibility to hidden.

Syntax

.HIDDEN name, name…

Description

Defines all symbols in the symbol list to have hidden visibility and is stored as STV_HIDDEN in the st_other member of the ELF symbol table entry.

.PROTECTED

Set symbol visibility to protected.

Syntax

.PROTECTED name, name…

Description

Defines all symbols in the symbol list to have protected visibility and is stored as STV_PROTECTED in the st_other member of the ELF symbol table entry.

.INTERNAL

Set symbol visibility to internal.

Syntax

.INTERNAL name, name…

Description

Defines all symbols in the symbol list to have internal visibility and is stored as STV_INTERNAL in the st_other member of the ELF symbol table entry.

Data allocation directives

.BYTE, .ASCII

Allocate 8-bit data.

Syntax

.BYTE expr, expr…
.ASCII expr, expr…

Description

Place the initialized 8-bit values in the expression list into memory at the location counter.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_BYTE.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3             00000000 4120736D      .BYTE "A small list of primes:"
                 00000004 616C6C20
                 00000008 6C697374
                 0000000C 206F6620
                 00000010 7072696D
                 00000014 65733A
   4             00000017 02030507      .BYTE 2, 3, 5, 7, 11, 13
                 0000001B 0B0D
   5                                 
   6                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.STRING, .ASCIZ

.STRING, .ASCIZ

Allocate string data.

Syntax

.STRING expr, expr…
.ASCIZ expr, expr…

Description

Place the initialized string values in the expression list into memory at the location counter, each string followed by a trailing zero byte.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_STRING.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ String is terminated by a zero byte
   4             00000000 49742073      .STRING "It simply works!"
                 00000004 696D706C
                 00000008 7920776F
                 0000000C 726B7321
                 00000010 00
   5                                 
   6                                     @ Each string is terminated by a zero byte
   7             00000011 53454747      .STRING "SEGGER", "The Embedded Experts"
                 00000015 45520054
                 00000019 68652045
                 0000001D 6D626564
                 00000021 64656420
                 00000025 45787065
                 00000029 72747300
   8                                 
   9                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.BYTE, .ASCII

.2BYTE

Allocate 16-bit data.

Syntax

.2BYTE expr, expr…

Description

Place the initialized 16-bit values in the expression list into memory at the location counter.

These directives do not force the location counter to be halfword aligned when placing the data, and no warning diagnostic is issued when the location counter is not correctly aligned.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_2BYTE.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ Data that is correctly aligned
   4             00000000 DEADBEEF      .2BYTE 0xADDE, 0xEFBE, 0xDEAD, 0xBEEF
                 00000004 ADDEEFBE
   5                                 
   6                                     @ Data that is not aligned on a halfword
   7             00000008               .SPACE 1
   8             00000009 DEADBEEF      .2BYTE 0xADDE, 0xEFBE, 0xDEAD, 0xBEEF
                 0000000D ADDEEFBE
   9                                 
  10                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.HWORD, .SHORT

.4BYTE

Allocate 32-bit data.

Syntax

.4BYTE expr, expr…

Description

Place the initialized 32-bit values in the expression list into memory at the location counter.

These directives do not force the location counter to be word aligned when placing the data, and do not issue a warning diagnostic when the location counter is not correctly aligned.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_4BYTE.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ Data that is correctly aligned
   4             00000000 DEADBEEF      .4BYTE 0xEFBEADDE, 0xDEADBEEF
                 00000004 EFBEADDE
   5                                 
   6                                     @ Data that is not aligned on a word
   7             00000008               .SPACE 1
   8             00000009 DEADBEEF      .4BYTE 0xEFBEADDE, 0xDEADBEEF
                 0000000D EFBEADDE
   9                                 
  10                                    .END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

.WORD, .INT, .LONG

.HWORD, .SHORT

Allocate 16-bit data.

Syntax

.HWORD expr, expr…
.SHORT expr, expr…

Description

Place the initialized 16-bit values in the expression list into memory at the location counter.

These directives do not force the location counter to be halfword aligned when placing the data, but a warning diagnostic is issued when the location counter is not correctly aligned.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_HWORD.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ Data that is correctly aligned
   4             00000000 DEADBEEF      .HWORD 0xADDE, 0xEFBE, 0xDEAD, 0xBEEF
                 00000004 ADDEEFBE
   5                                 
   6                                     @ Data that is not aligned on a halfword
   7             00000008               .SPACE 1
   8             00000009 DEADBEEF      .HWORD 0xADDE, 0xEFBE, 0xDEAD, 0xBEEF
                 0000000D ADDEEFBE
   9                                 
  10                                    .END

DIAGNOSTICS

GNU_HWORD.s:8: warning: 16-bit data does not fall on natural alignment at address 00000009
GNU_HWORD.s:8: warning: 16-bit data does not fall on natural alignment at address 0000000B
GNU_HWORD.s:8: warning: 16-bit data does not fall on natural alignment at address 0000000D
GNU_HWORD.s:8: warning: 16-bit data does not fall on natural alignment at address 0000000F

ASSEMBLY COMPLETE

No errors, 4 warnings, no remarks

See also

.2BYTE

.WORD, .INT, .LONG

Allocate 32-bit data.

Syntax

.WORD expr, expr…
.INT expr, expr…
.LONG expr, expr…

Description

Place the initialized 32-bit values in the expression list into memory at the location counter.

These directives do not force the location counter to be word aligned when placing the data, but a warning diagnostic is issued when the location counter is not correctly aligned.

Example

SEGGER Assembler V2.10    www.segger.com
GNU_WORD.s - Assembled Thu Nov  7 11:46:23 2019

   1                                    .DATA
   2                                 
   3                                     @ Data that is correctly aligned
   4             00000000 DEADBEEF      .WORD 0xEFBEADDE, 0xDEADBEEF
                 00000004 EFBEADDE
   5                                 
   6                                     @ Data that is not aligned on a word
   7             00000008               .SPACE 1
   8             00000009 DEADBEEF      .WORD 0xEFBEADDE, 0xDEADBEEF
                 0000000D EFBEADDE
   9                                 
  10                                    .END

DIAGNOSTICS

GNU_WORD.s:8: warning: 32-bit data does not fall on natural alignment at address 00000009
GNU_WORD.s:8: warning: 32-bit data does not fall on natural alignment at address 0000000D

ASSEMBLY COMPLETE

No errors, 2 warnings, no remarks

See also

.4BYTE

.INST

Allocate 16-bit or 32-bit instruction.

Syntax

.INST expr, expr…

Description

Place the initialized values in the expression list into memory at the location counter as instruction codes. For values that fit into 16 bits, a 16-bit instruction is generated, and for others a 32-bit instruction is generated.

.INST.N

Allocate 16-bit instruction.

Syntax

.INST.N expr, expr…

Description

Place the initialized 16-bit values in the expression list into memory at the location counter as instruction codes.

.INST.W

Allocate 32-bit instruction.

Syntax

.INST.W expr, expr…

Description

Place the initialized 32-bit values in the expression list into memory at the location counter as instruction codes.

Section directives

.ALIGN

Align location counter.

Syntax

.ALIGN align-power, fill-value, max-bytes

Description

The align-power expression, which must be absolute, is the power of two to align the location counter to. An align-power of 3, for instance, will ensure that the location counter is a multiple of 2³, i.e. 8.

The optional fill-value defines the filler byte to use when aligning the location counter. If omitted, a default value of is selected: the default value for code sections is a nop instruction and for other sections it is zero.

The optional max-bytes defines the maximum number of bytes inserted to align the location counter. If more than max-bytes bytes are required for alignment, no alignment is performed.

.P2ALIGN, .P2ALIGNW, .P2ALIGNL

Align location counter.

Syntax

.P2ALIGN align-power, fill-value, max-bytes
.P2ALIGNW align-power, fill-value, max-bytes
.P2ALIGNL align-power, fill-value, max-bytes

Description

The align-power expression, which must be absolute, is the power of two to align the location counter to. An align-power of 3, for instance, will ensure that the location counter is a multiple of 2³, i.e. 8.

The optional fill-value defines the filler value to use when aligning the location counter. If omitted, a default value of is selected: the default value for code sections is a nop instruction and for other sections it is zero. If it is specified, the fill value is a one-byte pattern for .P2ALIGN, a two-byte pattern for .P2ALIGNW, and a 4-byte pattern for .P2ALIGNL.

The optional max-bytes defines the maximum number of bytes inserted to align the location counter. If more than max-bytes bytes are required for alignment, no alignment is performed.

Listing directives

.LIST

Turn on listing.

Syntax

.LIST

Description

Each line subsequently assembled will be printed to the listing file.

.NOLIST

Turn off listing.

Syntax

.LIST

Description

Each line subsequently assembled will be not be printed to the listing file.

.TITLE

Set listing title.

Syntax

.TITLE string-expr

Description

Sets the title that is shown at the top of each page in the listing.

.SUBTTL

Set listing subtitle.

Syntax

.SUBTTL string-expr

Description

Sets the subtitle that is shown below the title at the top of each page in the listing.

Arm syntax

Mode directives

CODE16

Select Thumb instruction set.

Syntax

CODE16

Description

Selects the Thumb instruction set for following instructions.

Example

SEGGER Assembler V2.10    www.segger.com
ARM_CODE16.s - Assembled Thu Nov  7 11:46:23 2019

   1                                     AREA |.text|, CODE
   2                                 
   3                                     CODE16
   4                                 
   5             00000000 0120           MOVS R0, #1
   6             00000002 4018           ADDS R0, R0, R1
   7                                 
   8                                     END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

CODE32

CODE32

Select Arm instruction set.

Syntax

CODE32

Description

Selects the Arm instruction set for following instructions.

Example

SEGGER Assembler V2.10    www.segger.com
ARM_CODE32.s - Assembled Thu Nov  7 11:46:23 2019

   1                                     AREA |.text|, CODE
   2                                 
   3                                     CODE32
   4                                 
   5             00000000 0100B0E3       MOVS R0, #1
   6             00000004 010090E0       ADDS R0, R0, R1
   7                                 
   8                                     END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

See also

CODE16

Listing directives

TTL

Set listing title.

Syntax

TTL open-string

Description

Sets the title that is shown at the top of each page in the listing.

SUBT

Set listing subtitle.

Syntax

SUBT open-string

Description

Sets the subtitle that is shown below the title at the top of each page in the listing.

IAR syntax

Mode directives

ARM, CODE32

Select Arm instruction set.

Syntax

ARM
CODE32

Description

Selects the Arm instruction set for following instructions.

See also

THUMB, CODE16

CODE

Select default instruction set.

Syntax

CODE

Description

Selects the Arm or Thumb instruction set according to that specified on the command line by the -mthumb or -marm options. If no instruction set is specified on the command line, the instruction defaults to Thumb.

THUMB, CODE16

Select Thumb instruction set.

Syntax

THUMB
CODE16

Description

Selects the Thumb instruction set for following instructions.

See also

ARM, CODE32

Data allocation directives

DC8, DCB

Allocate 8-bit data.

Syntax

DC8 expr, expr…
DCB expr, expr…

Description

Place the initialized 8-bit values in the expression list into memory at the location counter.

Example

SEGGER Assembler V2.10    www.segger.com
IAR_DC8.s - Assembled Thu Nov  7 11:46:23 2019

   1                                     SECTION `.data`:DATA(2)
   2                                 
   3             00000000 4120736D       DCB "A small list of primes:"
                 00000004 616C6C20
                 00000008 6C697374
                 0000000C 206F6620
                 00000010 7072696D
                 00000014 65733A
   4             00000017 02030507       DC8  2, 3, 5, 7, 11, 13
                 0000001B 0B0D
   5                                 
   6                                     END

ASSEMBLY COMPLETE

No errors, no warnings, no remarks

DC16, DCW

Allocate 16-bit data.

Syntax

DC16 expr, expr…
DCW expr, expr…

Description

Place the initialized 16-bit values in the expression list into memory at the location counter.

DC24

Allocate 24-bit data.

Syntax

DC24 expr, expr…

Description

Place the initialized 32-bit values in the expression list into memory at the location counter.

DC32, DCD

Allocate 32-bit data.

Syntax

DC32 expr, expr…
DCD expr, expr…

Description

Place the initialized 32-bit values in the expression list into memory at the location counter.

DCI16, DCIW

Allocate 16-bit instruction.

Syntax

DCI16 expr, expr…
DCIW expr, expr…

Description

Place the initialized 16-bit values in the expression list into memory at the location counter as instruction codes.

DCI32, DCID

Allocate 32-bit instruction.

Syntax

DCI32 expr, expr…
DCID expr, expr…

Description

Place the initialized 32-bit values in the expression list into memory at the location counter as instruction codes.

DS8, DS

Allocate space for 8-bit data.

Syntax

DS8 expr
DS expr

Description

Allocate space for expr 8-bit bytes. For zero-data sections such as .bss, the space is allocated; for sections that have content, such as .text and .data, the allocated space is initialized with zero bytes.

DS16, DSW

Allocate space for 16-bit data.

Syntax

DS16 expr
DSW expr

Description

Allocate space for expr 16-bit elements. For zero-data sections such as .bss, the space is allocated; for sections that have content, such as .text and .data, the allocated space is initialized with zero bytes.

DS24

Allocate space for 24-bit data.

Syntax

DS24 expr

Description

Allocate space for expr 24-bit elements. For zero-data sections such as .bss, the space is allocated; for sections that have content, such as .text and .data, the allocated space is initialized with zero bytes.

DS32, DSD

Allocate space for 32-bit data.

Syntax

DS32 expr
DSD expr

Description

Allocate space for expr 32-bit elements. For zero-data sections such as .bss, the space is allocated; for sections that have content, such as .text and .data, the allocated space is initialized with zero bytes.

Instructions

Arm instructions

ADC

Description

Add with carry

Thumb syntax (16-bit, v4T)

ADC

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

ADC	Rd, Rn, #const	[2]
ADC	Rd, Rn, Rm, shift	[3]
ADCS	Rd, Rn, #const	[2]
ADCS	Rd, Rn, Rm, shift	[3]

Arm syntax (v4T)

ADC	Rd, Rn, #const	[4]
ADC	Rd, Rn, Rm, shift	[5]
ADCS	Rd, Rn, #const	[4]
ADCS	Rd, Rn, Rm, shift	[5]

Notes

[1] Rd, Rn must be R0…R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is $xx ROR 2n
[5] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

ADD

Description

Add

Thumb syntax (16-bit, v4T)

ADD	Rd, Rn	[1]
ADD	Rd, Rn, Rm	[2]
ADD	Rd, #0…255	[3]
ADD	Rd, Rn, #0…7	[4]
ADD	SP, SP, #0…508	[5]
ADD	Rd, SP, #0…1020	[6]
ADD	Rd, PC, #0…1020	[6]

Thumb syntax (32-bit, v6T2)

ADD	Rd, Rn, #0…4095	[7]
ADD	Rd, Rn, #const	[8]
ADD	Rd, Rn, Rm, shift	[9]
ADDS	Rd, Rn, #const	[8]
ADDS	Rd, Rn, Rm, shift	[9]

Arm syntax (v4T)

ADD	Rd, Rn, #const	[10]
ADD	Rd, Rn, Rm, shift	[11]
ADD	Rd, SP, Rm, shift	[12]
ADDS	Rd, Rn, #const	[13]
ADDS	Rd, Rn, Rm, shift	[11]
ADDS	Rd, SP, Rm, shift	[12]

Notes

[1] ordering Rd, Rn, Rd is also permitted
[2] Rd, Rn, Rm must be R0…R7
[3] Rd must be R0…R7
[4] Rd, Rn must be R0…R7
[5] offset a multiple of 4
[6] Rd must be R0…R7; offset a multiple of 4
[7] Rd ≠ PC; Rd ≠ SP
[8] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[9] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[10] Rd ≠ SP; const is $xx ROR 2n
[11] Rd, Rm ≠ PC; Rd, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX
[12] Rd, Rm ≠ PC; Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX
[13] Rd ≠ PC; Rd ≠ SP; const is $xx ROR 2n

ADDW

Description

Add

Thumb syntax (16-bit, v6T2)

ADDW

Rd, PC, #0…1020

[1]

Thumb syntax (32-bit, v6T2)

ADDW

Rd, Rn, #0…4095

[2]

Notes

[1] Rd must be R0…R7; offset a multiple of 4
[2] Rd ≠ PC; Rd ≠ SP

AND

Description

Bitwise and

Thumb syntax (16-bit, v4T)

AND

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

AND	Rd, Rn, #const	[2]
AND	Rd, Rn, Rm, shift	[3]
ANDS	Rd, Rn, #const	[2]
ANDS	Rd, Rn, Rm, shift	[3]

Arm syntax (v4T)

AND	Rd, Rn, #const	[4]
AND	Rd, Rn, Rm, shift	[5]
ANDS	Rd, Rn, #const	[4]
ANDS	Rd, Rn, Rm, shift	[5]

Notes

[1] Rd, Rn must be R0…R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is $xx ROR 2n
[5] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

ASR

Description

Arithmetic shift right

Thumb syntax (16-bit, v4T)

ASR	Rd, Rn	[1]
ASR	Rd, Rn, #1…32	[1]

Thumb syntax (32-bit, v6T2)

ASR	Rd, Rn, Rm	[2]
ASR	Rd, Rn, #1…32	[3]
ASRS	Rd, Rn, Rm	[2]
ASRS	Rd, Rn, #1…32	[3]

Arm syntax (v4T)

ASR	Rd, Rn, Rm	[4]
ASR	Rd, Rn, #1…32
ASRS	Rd, Rn, Rm	[4]
ASRS	Rd, Rn, #1…32

Notes

[1] Rd, Rn must be R0…R7
[2] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP
[3] Rd, Rn ≠ PC; Rd, Rn ≠ SP
[4] Rd, Rn, Rm ≠ PC

B

Description

Branch

Thumb syntax (16-bit, v4T)

B

Label

[1]

Thumb syntax (32-bit, v6T2)

B

Label

Arm syntax (v4T)

B

Label

Notes

[1] not permitted in an IT block

BCC

Description

Branch if no carry

Thumb syntax (16-bit, v4T)

BCC

Label

[1]

Thumb syntax (32-bit, v6T2)

BCC

Label

[1]

Notes

[1] not permitted in an IT block

BCS

Description

Branch if carry

Thumb syntax (16-bit, v4T)

BCS

Label

[1]

Thumb syntax (32-bit, v6T2)

BCS

Label

[1]

Notes

[1] not permitted in an IT block

BEQ

Description

Branch if equal

Thumb syntax (16-bit, v4T)

BEQ

Label

[1]

Thumb syntax (32-bit, v6T2)

BEQ

Label

[1]

Notes

[1] not permitted in an IT block

BFC

Description

Bitfield clear

Thumb syntax (32-bit, v6T2)

BFC

Rd, #lsb, #width

[1]

Arm syntax (v6T2)

BFC

Rd, #lsb, #width

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

BFI

Description

Bitfield insert

Thumb syntax (32-bit, v6T2)

BFI

Rd, Rn, #lsb, #width

[1]

Arm syntax (v6T2)

BFI

Rd, Rn, #lsb, #width

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

BGE

Description

Branch if greater or equal

Thumb syntax (16-bit, v4T)

BGE

Label

[1]

Thumb syntax (32-bit, v6T2)

BGE

Label

[1]

Notes

[1] not permitted in an IT block

BGT

Description

Branch if greater

Thumb syntax (16-bit, v4T)

BGT

Label

[1]

Thumb syntax (32-bit, v6T2)

BGT

Label

[1]

Notes

[1] not permitted in an IT block

BHI

Description

Branch if greater

Thumb syntax (16-bit, v4T)

BHI

Label

[1]

Thumb syntax (32-bit, v6T2)

BHI

Label

[1]

Notes

[1] not permitted in an IT block

BHS

Description

Branch if carry

Thumb syntax (16-bit, v4T)

BHS

Label

[1]

Thumb syntax (32-bit, v6T2)

BHS

Label

[1]

Notes

[1] not permitted in an IT block

BIC

Description

Bitwise clear

Thumb syntax (16-bit, v4T)

BIC

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

BIC	Rd, Rn, #const	[2]
BIC	Rd, Rn, Rm, shift	[3]
BICS	Rd, Rn, #const	[2]
BICS	Rd, Rn, Rm, shift	[3]

Arm syntax (v4T)

BIC	Rd, Rn, #const	[4]
BIC	Rd, Rn, Rm, shift	[5]
BICS	Rd, Rn, #const	[4]
BICS	Rd, Rn, Rm, shift	[5]

Notes

[1] Rd, Rn must be R0…R7
[2] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rd, Rn ≠ PC; const is $xx ROR 2n
[5] Rd, Rn, Rm ≠ PC; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

BKPT

Description

Breakpoint

Thumb syntax (16-bit, v5T)

BKPT

#0…255

Arm syntax (v5T)

BKPT

Rd, #0…65535

BL

Description

Branch link

Thumb syntax (32-bit, v4T)

BL

Label

Arm syntax (v4T)

BL

Label

BLE

Description

Branch if less than or equal

Thumb syntax (16-bit, v4T)

BLE

Label

[1]

Thumb syntax (32-bit, v6T2)

BLE

Label

[1]

Notes

[1] not permitted in an IT block

BLO

Description

Branch if no carry

Thumb syntax (16-bit, v4T)

BLO

Label

[1]

Thumb syntax (32-bit, v6T2)

BLO

Label

[1]

Notes

[1] not permitted in an IT block

BLS

Thumb syntax (16-bit, v4T)

BLS

Label

[1]

Thumb syntax (32-bit, v6T2)

BLS

Label

[1]

Notes

[1] not permitted in an IT block

BLT

Description

Branch is less than

Thumb syntax (16-bit, v4T)

BLT

Label

[1]

Thumb syntax (32-bit, v6T2)

BLT

Label

[1]

Notes

[1] not permitted in an IT block

BLX

Description

Branch link and exchange

Thumb syntax (16-bit, v5T)

BLX

Rd

[1]

Thumb syntax (32-bit, v4T)

BLX

Label

Arm syntax (v4T)

BLX	Rd	[1]
BLX	Label

Notes

[1] Rd ≠ PC; Rd ≠ SP

BMI

Description

Branch if negative

Thumb syntax (16-bit, v4T)

BMI

Label

[1]

Thumb syntax (32-bit, v6T2)

BMI

Label

[1]

Notes

[1] not permitted in an IT block

BNE

Description

Branch if not equal

Thumb syntax (16-bit, v4T)

BNE

Label

[1]

Thumb syntax (32-bit, v6T2)

BNE

Label

[1]

Notes

[1] not permitted in an IT block

BPL

Description

Branch is nonnegative

Thumb syntax (16-bit, v4T)

BPL

Label

[1]

Thumb syntax (32-bit, v6T2)

BPL

Label

[1]

Notes

[1] not permitted in an IT block

BVC

Description

Branch if no overflow

Thumb syntax (16-bit, v4T)

BVC

Label

[1]

Thumb syntax (32-bit, v6T2)

BVC

Label

[1]

Notes

[1] not permitted in an IT block

BVS

Description

Branch is overflow

Thumb syntax (16-bit, v4T)

BVS

Label

[1]

Thumb syntax (32-bit, v6T2)

BVS

Label

[1]

Notes

[1] not permitted in an IT block

BX

Description

Branch and exchange

Thumb syntax (16-bit, v4T)

BX

Rd

[1]

Arm syntax (v4T)

BX

Rd

Notes

[1] Rd ≠ PC; Rd ≠ SP

BXJ

Description

Branch and change to Jazelle state

Thumb syntax (32-bit, v6J)

BXJ

Rd

[1]

Arm syntax (v6J)

BXJ

Rd

[1]

Notes

[1] Rd ≠ PC; Rd ≠ SP

CBNZ

Description

Branch if nonzero

Thumb syntax (16-bit, v6T2)

CBNZ

Rd, Label

[1]

Notes

[1] not permitted in an IT block

CBZ

Description

Branch if zero

Thumb syntax (16-bit, v6T2)

CBZ

Rd, Label

[1]

Notes

[1] not permitted in an IT block

CDP

Description

Coprocessor data operation

Thumb syntax (32-bit, v6T2)

CDP

Pn, [#]0…15, CRx, CRy, CRz

Arm syntax (v6T2)

CDP

Pn, [#]0…15, CRx, CRy, CRz

CDP2

Description

Coprocessor data operation

Thumb syntax (32-bit, v6T2)

CDP2

Pn, [#]0…15, CRx, CRy, CRz

Arm syntax (v6T2)

CDP2

Pn, [#]0…15, CRx, CRy, CRz

CLREX

Description

Clear exclusive

Thumb syntax (32-bit, v6T2)

CLREX

Arm syntax (v6K)

CLREX

CLZ

Description

Count leading zeros

Thumb syntax (32-bit, v6T2)

CLZ

Rd, Rn

[1]

Arm syntax (v5T)

CLZ

Rd, Rn

[2]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP
[2] Rd, Rn ≠ PC

CMN

Description

Compare negated

Thumb syntax (16-bit, v4T)

CMN

Rn, Rm

[1]

Thumb syntax (32-bit, v6T2)

CMN	Rn, #const	[2]
CMN	Rn, Rm, shift	[3]

Arm syntax (v4T)

CMN	Rn, #const	[4]
CMN	Rn, Rm, shift	[5]

Notes

[1] Rn, Rm must be R0…R7
[2] Rn ≠ PC; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rn, Rm ≠ PC; Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rn ≠ PC; const is $xx ROR 2n
[5] Rn, Rm ≠ PC; Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

CMP

Description

Compare

Thumb syntax (16-bit, v4T)

CMP	Rn, Rm	[1]
CMP	Rn, #0…255	[2]

Thumb syntax (32-bit, v6T2)

CMP	Rn, #const	[3]
CMP	Rn, Rm, shift	[4]

Arm syntax (v4T)

CMP	Rn, #const	[5]
CMP	Rn, Rm, shift	[6]

Notes

[1] Rn, Rm ≠ PC; Rm ≠ SP
[2] Rn must be R0…R7
[3] Rn ≠ PC; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[4] Rn, Rm ≠ PC; Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[5] Rn ≠ PC; const is $xx ROR 2n
[6] Rn, Rm ≠ PC; Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

CPS

Description

Change processor state

Thumb syntax (32-bit, v)

CPS

#0…31

[1]

Arm syntax (v)

CPS

#0…31

[1]

Notes

[1] not permitted in an IT block

CPSID

Description

Change processor state

Thumb syntax (16-bit, v6)

CPSID

flags

[1]

Thumb syntax (32-bit, v)

CPSID	flags	[1]
CPSID	flags, #0…31	[1]

Arm syntax (v6)

CPSID	flags	[2]
CPSID	flags, #0…31	[2]

Notes

[1] flags is any combination of ’A’, ’I’, and ’F’; not permitted in an IT block
[2] flags is any combination of ’A’, ’I’, and ’F’

CPSIE

Description

Change processor state

Thumb syntax (16-bit, v6)

CPSIE

flags

[1]

Thumb syntax (32-bit, v)

CPSIE	flags	[1]
CPSIE	flags, #0…31	[1]

Arm syntax (v6)

CPSIE	flags	[2]
CPSIE	flags, #0…31	[2]

Notes

[1] flags is any combination of ’A’, ’I’, and ’F’; not permitted in an IT block
[2] flags is any combination of ’A’, ’I’, and ’F’

CPY

Description

Copy

Thumb syntax (16-bit, v6)

CPY

Rd, Rn

Arm syntax (v4T)

CPY

Rd, Rn

CRC32B

Description

CRC32 checksum byte

Thumb syntax (32-bit, v)

CRC32B

Rd, Rn, Rm

Arm syntax (v)

CRC32B

Rd, Rn, Rm

CRC32CB

Description

CRC32-C checksum byte

Thumb syntax (32-bit, v)

CRC32CB

Rd, Rn, Rm

Arm syntax (v)

CRC32CB

Rd, Rn, Rm

CRC32CH

Description

CRC32-C checksum halfword

Thumb syntax (32-bit, v)

CRC32CH

Rd, Rn, Rm

Arm syntax (v)

CRC32CH

Rd, Rn, Rm

CRC32CW

Description

CRC32-C checksum word

Thumb syntax (32-bit, v)

CRC32CW

Rd, Rn, Rm

Arm syntax (v)

CRC32CW

Rd, Rn, Rm

CRC32H

Description

CRC32 checksum halfword

Thumb syntax (32-bit, v)

CRC32H

Rd, Rn, Rm

Arm syntax (v)

CRC32H

Rd, Rn, Rm

CRC32W

Description

CRC32 checksum word

Thumb syntax (32-bit, v)

CRC32W

Rd, Rn, Rm

Arm syntax (v)

CRC32W

Rd, Rn, Rm

DBG

Description

Debug

Thumb syntax (32-bit, v6T2)

DBG

#0…15

Arm syntax (v6)

DBG

#0…15

DCPS1

Description

Debug switch to exception level 1

Thumb syntax (32-bit, v)

DCPS1

DCPS2

Description

Debug switch to exception level 2

Thumb syntax (32-bit, v)

DCPS2

DCPS3

Description

Debug switch to exception level 3

Thumb syntax (32-bit, v)

DCPS3

DMB

Description

Data memory barrier

Thumb syntax (32-bit, v6-M)

DMB

#0…15

Arm syntax (v)

DMB

#0…15

DSB

Description

Data synchronization barrier

Thumb syntax (32-bit, v6-M)

DSB

#0…15

Arm syntax (v)

DSB

#0…15

EOR

Description

Bitwise exclusive-or

Thumb syntax (16-bit, v4T)

EOR

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

EOR	Rd, Rn, #const	[2]
EOR	Rd, Rn, Rm, shift	[3]
EORS	Rd, Rn, #const	[2]
EORS	Rd, Rn, Rm, shift	[3]

Arm syntax (v4T)

EOR	Rd, Rn, #const	[4]
EOR	Rd, Rn, Rm, shift	[5]
EORS	Rd, Rn, #const	[4]
EORS	Rd, Rn, Rm, shift	[5]

Notes

[1] Rd, Rn must be R0…R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is $xx ROR 2n
[5] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

ERET

Description

Exception return

Thumb syntax (32-bit, v)

ERET

Arm syntax (v)

ERET

ESB

Description

Exception synchronization barrier

Thumb syntax (32-bit, v)

ESB

Arm syntax (v)

ESB

HLT

Description

Halt

Thumb syntax (16-bit, v)

HLT

#0…63

Arm syntax (v)

HLT

Rd, #0…65535

HVC

Description

Hypervisor call

Thumb syntax (32-bit, v)

HVC

#0…65535

Arm syntax (v)

HVC

Rd, #0…65535

ISB

Description

Instruction synchronization barrier

Thumb syntax (32-bit, v6-M)

ISB

#0…15

Arm syntax (v)

ISB

#0…15

IT

Description

If-Then

Thumb syntax (16-bit, v6T2)

IT

ITE

Description

If-Then-Else

Thumb syntax (16-bit, v6T2)

ITE

ITEE

Description

If-Then-Else-Else

Thumb syntax (16-bit, v6T2)

ITEE

ITEEE

Description

If-Then-Else-Else-Else

Thumb syntax (16-bit, v6T2)

ITEEE

ITEET

Description

If-Then-Else-Else-Then

Thumb syntax (16-bit, v6T2)

ITEET

ITET

Description

If-Then-Else-Then

Thumb syntax (16-bit, v6T2)

ITET

ITETE

Description

If-Then-Else-Then-Else

Thumb syntax (16-bit, v6T2)

ITETE

ITETT

Description

If-Then-Else-Then-Then

Thumb syntax (16-bit, v6T2)

ITETT

ITT

Description

If-Then-Then

Thumb syntax (16-bit, v6T2)

ITT

ITTE

Description

If-Then-Then-Else

Thumb syntax (16-bit, v6T2)

ITTE

ITTEE

Description

If-Then-Then-Else-Else

Thumb syntax (16-bit, v6T2)

ITTEE

ITTET

Description

If-Then-Then-Else-Then

Thumb syntax (16-bit, v6T2)

ITTET

ITTT

Description

If-Then-Then-Then

Thumb syntax (16-bit, v6T2)

ITTT

ITTTE

Description

If-Then-Then-Then-Else

Thumb syntax (16-bit, v6T2)

ITTTE

ITTTT

Description

If-Then-Then-Then-Then

Thumb syntax (16-bit, v6T2)

ITTTT

LDA

Description

Load-acquire word

Thumb syntax (32-bit, v)

LDA

Rd, [Rn]

[1]

Arm syntax (v)

LDA

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

LDAB

Description

Load-acquire byte

Thumb syntax (32-bit, v)

LDAB

Rd, [Rn]

[1]

Arm syntax (v)

LDAB

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

LDAEX

Description

Load-acquire word exclusive

Thumb syntax (32-bit, v)

LDAEX

Rd, [Rn]

[1]

Arm syntax (v)

LDAEX

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

LDAEXB

Description

Load-acquire byte exclusive

Thumb syntax (32-bit, v)

LDAEXB

Rd, [Rn]

[1]

Arm syntax (v)

LDAEXB

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

LDAEXD

Description

Load-acquire doubleword exclusive

Thumb syntax (32-bit, v)

LDAEXD

Rd1, Rd2, [Rn]

[1]

Arm syntax (v)

LDAEXD

Rd1, Rd2, [Rn]

[2]

Notes

[1] Rd1, Rd2, Rn ≠ PC; Rd1 ≠ Rd2
[2] Rd1, Rd2, Rn ≠ PC; Rd1 ≠ Rd2; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register

LDAEXH

Description

Load-acquire halfword exclusive

Thumb syntax (32-bit, v)

LDAEXH

Rd, [Rn]

[1]

Arm syntax (v)

LDAEXH

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

LDAH

Description

Load-acquire halfword

Thumb syntax (32-bit, v)

LDAH

Rd, [Rn]

[1]

Arm syntax (v)

LDAH

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

LDM

Description

Load multiple

Thumb syntax (16-bit, v4T)

LDM	SP!, {Rn, Rm…}
LDM	Rd, {Rn, Rm…}	[1]
LDM	Rd, {Rn, Rm…}	[2]
LDM	Rd!, {Rn, Rm…}	[1]

Thumb syntax (32-bit, v6T2)

LDM	Rd, {Rn, Rm…}	[2]
LDM	Rd!, {Rn, Rm…}	[2]

Arm syntax (v4T)

LDM	Rd, {Rn, Rm…}	[2]
LDM	Rd!, {Rn, Rm…}	[2]

Notes

[1] Rd must be R0…R7; Rd ≠ PC
[2] Rd ≠ PC

LDMDA

Description

Load multiple decrement after

Thumb syntax (16-bit, v4T)

LDMDA

Rd, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

LDMDA	Rd, {Rn, Rm…}
LDMDA	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

LDMDA	Rd, {Rn, Rm…}	[1]
LDMDA	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

LDMDB

Description

Load multiple decrement before

Thumb syntax (32-bit, v6T2)

LDMDB	Rd, {Rn, Rm…}	[1]
LDMDB	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

LDMDB	Rd, {Rn, Rm…}	[1]
LDMDB	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

LDMEA

Description

Load multiple empty ascending

Thumb syntax (32-bit, v6T2)

LDMEA	Rd, {Rn, Rm…}	[1]
LDMEA	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

LDMEA	Rd, {Rn, Rm…}	[1]
LDMEA	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

LDMED

Description

Load multiple empty descending

Thumb syntax (16-bit, v4T)

LDMED

Rd, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

LDMED	Rd, {Rn, Rm…}
LDMED	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

LDMED	Rd, {Rn, Rm…}	[1]
LDMED	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

LDMFA

Description

Load multiple full ascending

Thumb syntax (16-bit, v4T)

LDMFA

Rd, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

LDMFA	Rd, {Rn, Rm…}
LDMFA	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

LDMFA	Rd, {Rn, Rm…}	[1]
LDMFA	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

LDMFD

Description

Load multiple full descending

Thumb syntax (16-bit, v4T)

LDMFD	SP!, {Rn, Rm…}
LDMFD	Rd, {Rn, Rm…}	[1]
LDMFD	Rd, {Rn, Rm…}	[2]
LDMFD	Rd!, {Rn, Rm…}	[1]

Thumb syntax (32-bit, v6T2)

LDMFD	Rd, {Rn, Rm…}	[2]
LDMFD	Rd!, {Rn, Rm…}	[2]

Arm syntax (v4T)

LDMFD	Rd, {Rn, Rm…}	[2]
LDMFD	Rd!, {Rn, Rm…}	[2]

Notes

[1] Rd must be R0…R7; Rd ≠ PC
[2] Rd ≠ PC

LDMIA

Description

Load multiple increment after

Thumb syntax (16-bit, v4T)

LDMIA	SP!, {Rn, Rm…}
LDMIA	Rd, {Rn, Rm…}	[1]
LDMIA	Rd, {Rn, Rm…}	[2]
LDMIA	Rd!, {Rn, Rm…}	[1]

Thumb syntax (32-bit, v6T2)

LDMIA	Rd, {Rn, Rm…}	[2]
LDMIA	Rd!, {Rn, Rm…}	[2]

Arm syntax (v4T)

LDMIA	Rd, {Rn, Rm…}	[2]
LDMIA	Rd!, {Rn, Rm…}	[2]

Notes

[1] Rd must be R0…R7; Rd ≠ PC
[2] Rd ≠ PC

LDMIB

Description

Load multiple increment before

Thumb syntax (16-bit, v4T)

LDMIB

Rd, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

LDMIB	Rd, {Rn, Rm…}
LDMIB	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

LDMIB	Rd, {Rn, Rm…}	[1]
LDMIB	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

LDR

Description

Load word

Thumb syntax (16-bit, v4T)

LDR	Rd, [Rn, #0…124]	[1]
LDR	Rd, [SP, #0…1020]	[2]
LDR	Rd, [PC, #0…1020]	[2]
LDR	Rd, [Rn, Rm]	[3]
LDR	Rd, #Label

Thumb syntax (32-bit, v6T2)

LDR	Rd, [Rn, #−255…4095]
LDR	Rd, [PC, #−4095…4095]
LDR	Rd, [Rn, #−255…255]!	[4]
LDR	Rd, [Rn], #−255…255	[4]
LDR	Rd, [Rn, Rm]	[5]
LDR	Rd, [Rn, Rm, LSL #1…3]	[6]
LDR	Rd, #Label

Arm syntax (v4T)

LDR	Rd, [Rn, #−4095…4095]
LDR	Rd, [Rn, #−4095…4095]!	[4]
LDR	Rd, [Rn], #−4095…4095	[4]
LDR	Rd, [Rn], ±Rm, shift	[7]
LDR	Rd, [Rn, ±Rm]	[8]
LDR	Rd, [Rn, ±Rm]!	[7]

Notes

[1] Rd, Rn must be R0…R7; offset a multiple of 4
[2] offset a multiple of 4
[3] Rd, Rn, Rm must be R0…R7
[4] Rn ≠ PC; Rd ≠ Rn
[5] Rn, Rm ≠ PC; Rm ≠ SP
[6] Rn, Rm ≠ PC; Rm ≠ SP; LSL #0 is also permitted
[7] Rn, Rm ≠ PC; Rm ≠ SP; Rd ≠ Rn
[8] Rm ≠ PC; Rm ≠ SP

LDRB

Description

Load byte

Thumb syntax (16-bit, v4T)

LDRB	Rd, [Rn, #0…31]	[1]
LDRB	Rd, [Rn, Rm]	[2]

Thumb syntax (32-bit, v6T2)

LDRB	Rd, [Rn, #−255…4095]	[3]
LDRB	Rd, [PC, #−4095…4095]	[3]
LDRB	Rd, [Rn, #−255…255]!	[4]
LDRB	Rd, [Rn], #−255…255	[4]
LDRB	Rd, [Rn, Rm, LSL #1…3]	[5]

Arm syntax (v4T)

LDRB	Rd, [Rn, #−4095…4095]	[3]
LDRB	Rd, [Rn, #−4095…4095]!	[4]
LDRB	Rd, [Rn], #−4095…4095	[4]
LDRB	Rd, [Rn], ±Rm, shift	[6]
LDRB	Rd, [Rn, ±Rm]	[7]
LDRB	Rd, [Rn, ±Rm]!	[6]

Notes

[1] Rd, Rn must be R0…R7; Rd ≠ PC; Rd ≠ SP
[2] Rd, Rn, Rm must be R0…R7
[3] Rd ≠ PC; Rd ≠ SP
[4] Rd, Rn ≠ PC; Rd ≠ SP; Rd ≠ Rn
[5] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; LSL #0 is also permitted
[6] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; Rd ≠ Rn
[7] Rd, Rm ≠ PC; Rd, Rm ≠ SP

LDRBT

Description

Load byte, user mode

Thumb syntax (32-bit, v6T2)

LDRBT

Rd, [Rn, #0…255]

[1]

Arm syntax (v4T)

LDRBT	Rd, [Rn], #−4095…4095	[2]
LDRBT	Rd, [Rn], ±Rm, shift	[3]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP
[2] Rd, Rn ≠ PC; Rd ≠ SP; Rd ≠ Rn
[3] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; Rd ≠ Rn

LDRD

Description

Load doubleword

Thumb syntax (32-bit, v6T2)

LDRD	Rd1, Rd2, [Rn, #−1020…1020]	[1]
LDRD	Rd1, Rd2, [Rn, #−1020…1020]!	[2]
LDRD	Rd1, Rd2, [Rn], #−1020…1020	[2]

Arm syntax (v)

LDRD	Rd1, Rd2, [Rn, #−255…255]	[3]
LDRD	Rd1, Rd2, [Rn, #−255…255]!	[4]
LDRD	Rd1, Rd2, [Rn], #−255…255	[4]
LDRD	Rd1, Rd2, [Rn, ±Rm]	[5]
LDRD	Rd1, Rd2, [Rn, ±Rm]!	[6]
LDRD	Rd1, Rd2, [Rn], ±Rm	[6]

Notes

[1] Rd1, Rd2 ≠ PC; Rd1, Rd2 ≠ SP; Rd1 ≠ Rd2; offset a multiple of 4
[2] Rd1, Rd2, Rn ≠ PC; Rd1, Rd2 ≠ SP; Rd1 ≠ Rd2 ≠ Rn; offset a multiple of 4
[3] Rd1, Rd2 ≠ PC; Rd2 ≠ SP; Rd1 ≠ Rd2; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register
[4] Rd1, Rd2, Rn ≠ PC; Rd2 ≠ SP; Rd1 ≠ Rd2 ≠ Rn; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register
[5] Rd1, Rd2, Rm ≠ PC; Rd2, Rm ≠ SP; Rd1 ≠ Rd2 ≠ Rm; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register
[6] Rd1, Rd2, Rn, Rm ≠ PC; Rd2, Rm ≠ SP; Rd1 ≠ Rd2 ≠ Rn; Rd1 ≠ Rd2 ≠ Rm; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register

LDREX

Description

Load word exclusive

Thumb syntax (32-bit, v6T2)

LDREX

Rd, [Rn, #0…1020]

[1]

Arm syntax (v6)

LDREX

Rd, [Rn]

[2]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP; offset a multiple of 4
[2] Rd, Rn ≠ PC; Rd ≠ SP

LDREXB

Description

Load byte exclusive

Thumb syntax (32-bit, v6T2)

LDREXB

Rd, [Rn]

[1]

Arm syntax (v6)

LDREXB

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

LDREXD

Description

Load doubleword exclusive

Thumb syntax (32-bit, v)

LDREXD

Rd1, Rd2, [Rn]

[1]

Arm syntax (v)

LDREXD

Rd1, Rd2, [Rn]

[2]

Notes

[1] Rd1, Rd2, Rn ≠ PC; Rd1, Rd2 ≠ SP; Rd1 ≠ Rd2
[2] Rd1, Rd2, Rn ≠ PC; Rd1, Rd2 ≠ SP; Rd1 ≠ Rd2; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register

LDREXH

Description

Load halfword exclusive

Thumb syntax (32-bit, v6T2)

LDREXH

Rd, [Rn]

[1]

Arm syntax (v6)

LDREXH

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

LDRH

Description

Load halfword

Thumb syntax (16-bit, v4T)

LDRH	Rd, [Rn, #0…62]	[1]
LDRH	Rd, [Rn, Rm]	[2]

Thumb syntax (32-bit, v6T2)

LDRH	Rd, [Rn, #−255…4095]	[3]
LDRH	Rd, [PC, #−4095…4095]	[4]
LDRH	Rd, [Rn, #−255…255]!	[5]
LDRH	Rd, [Rn], #−255…255	[5]
LDRH	Rd, [Rn, Rm]	[6]
LDRH	Rd, [Rn, Rm, LSL #1…3]	[7]

Arm syntax (v4T)

LDRH	Rd, [Rn, #−255…255]	[4]
LDRH	Rd, [Rn, #−255…255]!	[5]
LDRH	Rd, [Rn], #−255…255	[5]
LDRH	Rd, [Rn, ±Rm]	[8]
LDRH	Rd, [Rn, ±Rm]!	[9]
LDRH	Rd, [Rn], ±Rm	[9]

Notes

[1] Rd, Rn must be R0…R7; offset a multiple of 2
[2] Rd, Rn, Rm must be R0…R7
[3] Rd, Rn ≠ PC; Rd ≠ SP
[4] Rd ≠ PC; Rd ≠ SP
[5] Rd, Rn ≠ PC; Rd ≠ SP; Rd ≠ Rn
[6] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP
[7] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; LSL #0 is also permitted
[8] Rd, Rm ≠ PC; Rd, Rm ≠ SP
[9] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; Rd ≠ Rn

LDRHT

Description

Load halfword, user mode

Thumb syntax (32-bit, v6T2)

LDRHT

Rd, [Rn, #0…255]

[1]

Arm syntax (v6T2)

LDRHT	Rd, [Rn], #−255…255	[2]
LDRHT	Rd, [Rn], ±Rm	[3]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP
[2] Rd, Rn ≠ PC; Rd ≠ SP; Rd ≠ Rn
[3] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; Rd ≠ Rn

LDRSB

Description

Load sign-extended byte

Thumb syntax (16-bit, v4T)

LDRSB

Rd, [Rn, Rm]

[1]

Thumb syntax (32-bit, v6T2)

LDRSB	Rd, [Rn, #−255…4095]	[2]
LDRSB	Rd, [PC, #−4095…4095]	[3]
LDRSB	Rd, [Rn, #−255…255]!	[4]
LDRSB	Rd, [Rn], #−255…255	[4]
LDRSB	Rd, [Rn, Rm, LSL #1…3]	[5]

Arm syntax (v4T)

LDRSB	Rd, [Rn, #−255…255]	[3]
LDRSB	Rd, [Rn, #−255…255]!	[4]
LDRSB	Rd, [Rn], #−255…255	[4]
LDRSB	Rd, [Rn, ±Rm]	[6]
LDRSB	Rd, [Rn, ±Rm]!	[7]
LDRSB	Rd, [Rn], ±Rm	[7]

Notes

[1] Rd, Rn, Rm must be R0…R7
[2] Rd, Rn ≠ PC; Rd ≠ SP
[3] Rd ≠ PC; Rd ≠ SP
[4] Rd, Rn ≠ PC; Rd ≠ SP; Rd ≠ Rn
[5] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; LSL #0 is also permitted
[6] Rd, Rm ≠ PC; Rd, Rm ≠ SP
[7] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; Rd ≠ Rn

LDRSBT

Description

Load sign-extended byte, user mode

Thumb syntax (32-bit, v6T2)

LDRSBT

Rd, [Rn, #0…255]

[1]

Arm syntax (v6T2)

LDRSBT	Rd, [Rn], #−255…255	[2]
LDRSBT	Rd, [Rn], ±Rm	[3]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP
[2] Rd, Rn ≠ PC; Rd ≠ SP; Rd ≠ Rn
[3] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; Rd ≠ Rn

LDRSH

Description

Load sign-extended halfword

Thumb syntax (16-bit, v4T)

LDRSH

Rd, [Rn, Rm]

[1]

Thumb syntax (32-bit, v6T2)

LDRSH	Rd, [Rn, #−255…4095]	[2]
LDRSH	Rd, [PC, #−4095…4095]	[3]
LDRSH	Rd, [Rn, #−255…255]!	[2]
LDRSH	Rd, [Rn], #−255…255	[2]
LDRSH	Rd, [Rn, Rm, LSL #1…3]	[4]

Arm syntax (v4T)

LDRSH	Rd, [Rn, #−255…255]	[3]
LDRSH	Rd, [Rn, #−255…255]!	[2]
LDRSH	Rd, [Rn], #−255…255	[2]
LDRSH	Rd, [Rn, ±Rm]	[5]
LDRSH	Rd, [Rn, ±Rm]!	[6]
LDRSH	Rd, [Rn], ±Rm	[6]

Notes

[1] Rd, Rn, Rm must be R0…R7
[2] Rd, Rn ≠ PC; Rd ≠ SP; Rd ≠ Rn
[3] Rd ≠ PC; Rd ≠ SP
[4] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; LSL #0 is also permitted
[5] Rd, Rm ≠ PC; Rd, Rm ≠ SP
[6] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; Rd ≠ Rn

LDRSHT

Description

Load sign-extended halfword, user mode

Thumb syntax (32-bit, v6T2)

LDRSHT

Rd, [Rn, #0…255]

[1]

Arm syntax (v6T2)

LDRSHT	Rd, [Rn], #−255…255	[2]
LDRSHT	Rd, [Rn], ±Rm	[3]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP
[2] Rd, Rn ≠ PC; Rd ≠ SP; Rd ≠ Rn
[3] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; Rd ≠ Rn

LDRT

Description

Load word, user mode

Thumb syntax (32-bit, v6T2)

LDRT

Rd, [Rn, #0…255]

[1]

Arm syntax (v4T)

LDRT	Rd, [Rn], #−4095…4095	[2]
LDRT	Rd, [Rn], ±Rm, shift	[3]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP
[2] Rd, Rn ≠ PC; Rd ≠ SP; Rd ≠ Rn
[3] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; Rd ≠ Rn

LSL

Description

Logical shift left

Thumb syntax (16-bit, v4T)

LSL	Rd, Rn	[1]
LSL	Rd, Rn, #0…31	[1]

Thumb syntax (32-bit, v6T2)

LSL	Rd, Rn, Rm	[2]
LSL	Rd, Rn, #0…31	[3]
LSLS	Rd, Rn, Rm	[2]
LSLS	Rd, Rn, #0…31	[3]

Arm syntax (v4T)

LSL	Rd, Rn, Rm	[2]
LSL	Rd, Rn, #0…31	[3]
LSLS	Rd, Rn, Rm	[2]
LSLS	Rd, Rn, #0…31	[3]

Notes

[1] Rd, Rn must be R0…R7
[2] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP
[3] Rd, Rn ≠ PC; Rd, Rn ≠ SP

LSR

Description

Logical shift right

Thumb syntax (16-bit, v4T)

LSR	Rd, Rn	[1]
LSR	Rd, Rn, #1…32	[1]

Thumb syntax (32-bit, v6T2)

LSR	Rd, Rn, Rm	[2]
LSR	Rd, Rn, #1…32	[3]
LSRS	Rd, Rn, Rm	[2]
LSRS	Rd, Rn, #1…32	[3]

Arm syntax (v4T)

LSR	Rd, Rn, Rm	[2]
LSR	Rd, Rn, #1…32	[3]
LSRS	Rd, Rn, Rm	[2]
LSRS	Rd, Rn, #1…32	[3]

Notes

[1] Rd, Rn must be R0…R7
[2] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP
[3] Rd, Rn ≠ PC; Rd, Rn ≠ SP

MCR

Description

Move register to coprocessor

Thumb syntax (32-bit, v6T2)

MCR

Pn, [#]0…7, Rn, CRx, CRy, [[#]0…7]

[1]

Arm syntax (v4T)

MCR

Pn, [#]0…7, Rn, CRx, CRy, [[#]0…7]

[1]

Notes

[1] Rm ≠ PC; Rm ≠ SP

MCR2

Description

Move register to coprocessor

Thumb syntax (32-bit, v6T2)

MCR2

Pn, [#]0…7, Rn, CRx, CRy, [[#]0…7]

[1]

Arm syntax (v5T)

MCR2

Pn, [#]0…7, Rn, CRx, CRy, [[#]0…7]

[1]

Notes

[1] Rm ≠ PC; Rm ≠ SP

MCRR

Description

Move registers to coprocessor

Thumb syntax (32-bit, v6T2)

MCRR

Pn, [#]0…15, Rn, Rm, CRx, CRy

Arm syntax (v4T)

MCRR

Pn, [#]0…15, Rn, Rm, CRx, CRy

MCRR2

Description

Move registers to coprocessor

Thumb syntax (32-bit, v6T2)

MCRR2

Pn, [#]0…15, Rn, Rm, CRx, CRy

[1]

Arm syntax (v6T2)

MCRR2

Pn, [#]0…15, Rn, Rm, CRx, CRy

[1]

Notes

[1] Rn ≠ PC; Rn ≠ SP

MLA

Description

Multiply and add

Thumb syntax (32-bit, v6T2)

MLA

Rd, Rn, Rm, Ra

[1]

Arm syntax (v4T)

MLA	Rd, Rn, Rm, Ra	[2]
MLAS	Rd, Rn, Rm, Ra	[2]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP
[2] Rd, Rn, Rm, Ra ≠ PC; Rd ≠ Rn

MLS

Description

Multiply and subtract

Thumb syntax (32-bit, v6T2)

MLS

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

MLS

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

MOV

Description

Move

Thumb syntax (16-bit, v4T)

MOV	*** Unknown (0)
MOV	Rd, Rn
MOV	Rd, Rn	[1]
MOV	Rd, #0	[2]

Thumb syntax (32-bit, v6T2)

MOV	Rd, #0…65535	[3]
MOV	Rd, #const	[4]
MOV	Rd, Rn, shift	[5]
MOVS	Rd, #const	[4]
MOVS	Rd, Rn, shift	[6]

Arm syntax (v4T)

MOV	Rd, #0…65535	[3]
MOV	Rd, #const	[7]
MOV	Rd, Rn, shift	[8]
MOVS	Rd, #const	[7]
MOVS	Rd, Rn, shift	[9]

Notes

[1] Rd, Rn must be R0…R7
[2] Rd must be R0…R7
[3] Rd ≠ PC; Rd ≠ SP
[4] Rd ≠ PC; Rd ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[5] Rd, Rn ≠ PC; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[6] Rd, Rn ≠ PC; Rd, Rn ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[7] Rd ≠ PC; Rd ≠ SP; const is $xx ROR 2n
[8] shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX
[9] Rd, Rn ≠ PC; Rd, Rn ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

MOVS

Thumb syntax (32-bit, v6T2)

MOVS	Rd, #const	[1]
MOVS	Rd, Rn, shift	[2]

Arm syntax (v4T)

MOVS	Rd, #const	[3]
MOVS	Rd, Rn, shift	[4]

Notes

[1] Rd ≠ PC; Rd ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[2] Rd, Rn ≠ PC; Rd, Rn ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[3] Rd ≠ PC; Rd ≠ SP; const is $xx ROR 2n
[4] Rd, Rn ≠ PC; Rd, Rn ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

MOVT

Description

Move top

Thumb syntax (32-bit, v6T2)

MOVT

Rd, #0…65535

[1]

Notes

[1] Rd ≠ PC; Rd ≠ SP

MOVW

Description

Move

Thumb syntax (32-bit, v6T2)

MOVW

Rd, #0…65535

[1]

Arm syntax (v6T2)

MOVW

Rd, #0…65535

[1]

Notes

[1] Rd ≠ PC; Rd ≠ SP

MRC

Description

Move coprocessor to register

Thumb syntax (32-bit, v6T2)

MRC

Pn, [#]0…7, Rn, CRx, CRy, [[#]0…7]

[1]

Arm syntax (v4T)

MRC

Pn, [#]0…7, Rn, CRx, CRy, [[#]0…7]

Notes

[1] Rm ≠ PC; Rm ≠ SP

MRC2

Description

Move coprocessor to register

Thumb syntax (32-bit, v6T2)

MRC2

Pn, [#]0…7, Rn, CRx, CRy, [[#]0…7]

[1]

Arm syntax (v5T)

MRC2

Pn, [#]0…7, Rn, CRx, CRy, [[#]0…7]

Notes

[1] Rm ≠ SP

MRRC

Description

Move coprocessor to registers

Thumb syntax (32-bit, v6T2)

MRRC

Pn, [#]0…15, Rn, Rm, CRx, CRy

Arm syntax (v4T)

MRRC

Pn, [#]0…15, Rn, Rm, CRx, CRy

MRRC2

Description

Move coprocessor to registers

Thumb syntax (32-bit, v6T2)

MRRC2

Pn, [#]0…15, Rn, Rm, CRx, CRy

[1]

Arm syntax (v6T2)

MRRC2

Pn, [#]0…15, Rn, Rm, CRx, CRy

[1]

Notes

[1] Rn ≠ PC; Rn ≠ SP

MRS

Description

Move system register to register

Thumb syntax (32-bit, v6T2)

MRS

Rd, SysReg

[1]

Arm syntax (v4T)

MRS

Rd, SysReg

[1]

Notes

[1] Rd ≠ PC; Rd ≠ SP

MSR

Description

Move register to system register

Thumb syntax (32-bit, v6T2)

MSR

SysReg, Rn

[1]

Arm syntax (v4T)

MSR	SysReg, Rn	[1]
MSR	SysReg, #0…4095

Notes

[1] Rn ≠ PC; Rn ≠ SP

MUL

Description

Multiply

Thumb syntax (16-bit, v4T)

MUL

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

MUL

Rd, Rn, Rm

[2]

Arm syntax (v4T)

MUL	Rd, Rn, Rm	[3]
MULS	Rd, Rn, Rm	[3]

Notes

[1] Rd, Rn must be R0…R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP
[3] Rd, Rn, Rm ≠ PC; Rd ≠ Rn

MVN

Description

Move not

Thumb syntax (16-bit, v4T)

MVN

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

MVN	Rd, #const	[2]
MVN	Rd, Rn, shift	[3]
MVNS	Rd, #const	[2]
MVNS	Rd, Rn, shift	[3]

Arm syntax (v4T)

MVN	Rd, #const	[4]
MVN	Rd, Rn, shift	[5]
MVNS	Rd, #const	[4]
MVNS	Rd, Rn, shift	[5]

Notes

[1] Rd, Rn must be R0…R7
[2] Rd ≠ PC; Rd ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rd, Rn ≠ PC; Rd, Rn ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is $xx ROR 2n
[5] Rd, Rn ≠ PC; Rd, Rn ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

NEG

Description

Negate

Thumb syntax (16-bit, v4T)

NEG

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

NEG	Rd, Rn	[2]
NEGS	Rd, Rn	[2]

Arm syntax (v4T)

NEG	Rd, Rn	[2]
NEGS	Rd, Rn	[2]

Notes

[1] Rd, Rn must be R0…R7
[2] Rd, Rn ≠ PC; Rd, Rn ≠ SP

NOP

Description

No operation

Thumb syntax (16-bit, v6-M)

NOP

Thumb syntax (32-bit, v6T2)

NOP

Arm syntax (v4T)

NOP

ORN

Description

Bitwise or-not

Thumb syntax (32-bit, v6T2)

ORN	Rd, Rn, #const	[1]
ORN	Rd, Rn, Rm, shift	[2]
ORNS	Rd, Rn, #const	[1]
ORNS	Rd, Rn, Rm, shift	[2]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[2] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX

ORR

Description

Bitwise or

Thumb syntax (16-bit, v4T)

ORR

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

ORR	Rd, Rn, #const	[2]
ORR	Rd, Rn, Rm, shift	[3]
ORRS	Rd, Rn, #const	[2]
ORRS	Rd, Rn, Rm, shift	[3]

Arm syntax (v4T)

ORR	Rd, Rn, #const	[4]
ORR	Rd, Rn, Rm, shift	[5]
ORRS	Rd, Rn, #const	[4]
ORRS	Rd, Rn, Rm, shift	[5]

Notes

[1] Rd, Rn must be R0…R7; ordering Rd, Rn, Rd is also permitted
[2] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is $xx ROR 2n
[5] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

PKHBT

Description

Pack halfword

Thumb syntax (32-bit, v7E-M)

PKHBT

Rd, Rn, Rm, shift

[1]

Arm syntax (v)

PKHBT

Rd, Rn, Rm, shift

[2]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[2] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

PKHTB

Description

Pack halfword

Thumb syntax (32-bit, v7E-M)

PKHTB

Rd, Rn, Rm, shift

[1]

Arm syntax (v)

PKHTB

Rd, Rn, Rm, shift

[2]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[2] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

PLD

Description

Preload data

Thumb syntax (32-bit, v6T2)

PLD	[Rd, #−4095…4095]
PLD	Rd, [Rn, Rm, LSL #1…3]	[1]

Arm syntax (v6T2)

PLD

[Rd, #−4095…4095]

Notes

[1] Rd ≠ PC; LSL #0 is also permitted

PLDW

Description

Preload data, write invalidate

Thumb syntax (32-bit, v6T2)

PLDW	[Rd, #−255…4095]	[1]
PLDW	Rd, [Rn, Rm, LSL #1…3]	[2]

Arm syntax (v6T2)

PLDW

[Rd, #−4095…4095]

[1]

Notes

[1] Rd ≠ PC
[2] Rd ≠ PC; LSL #0 is also permitted

PLI

Description

Preload instruction

Thumb syntax (32-bit, v6T2)

PLI	[Rd, #−4095…4095]
PLI	Rd, [Rn, Rm, LSL #1…3]	[1]

Arm syntax (v6T2)

PLI

[Rd, #−4095…4095]

Notes

[1] Rd ≠ PC; LSL #0 is also permitted

POP

Description

Pop registers

Thumb syntax (16-bit, v4T)

POP

{Rn, Rm…}

Thumb syntax (32-bit, v6T2)

POP

{Rn, Rm…}

Arm syntax (v4T)

POP

{Rn, Rm…}

PUSH

Description

Push registers

Thumb syntax (16-bit, v4T)

PUSH

{Rn, Rm…}

Thumb syntax (32-bit, v6T2)

PUSH

{Rn, Rm…}

Arm syntax (v4T)

PUSH

{Rn, Rm…}

QADD

Description

Signed add, saturating

Thumb syntax (32-bit, v6T2)

QADD

Rd, Rn, Rm

[1]

Arm syntax (v)

QADD

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

QADD16

Description

Signed parallel halfword add, saturating

Thumb syntax (32-bit, v6T2)

QADD16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

QADD16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

QADD8

Description

Signed parallel byte add, saturating

Thumb syntax (32-bit, v6T2)

QADD8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

QADD8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

QASX

Thumb syntax (32-bit, v6T2)

QASX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

QASX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

QDADD

Thumb syntax (32-bit, v6T2)

QDADD

Rd, Rn, Rm

[1]

Arm syntax (v)

QDADD

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

QDSUB

Thumb syntax (32-bit, v6T2)

QDSUB

Rd, Rn, Rm

[1]

Arm syntax (v)

QDSUB

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

QSAX

Thumb syntax (32-bit, v6T2)

QSAX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

QSAX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

QSUB

Description

Signed subtract, saturating

Thumb syntax (32-bit, v6T2)

QSUB

Rd, Rn, Rm

[1]

Arm syntax (v)

QSUB

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

QSUB16

Description

Signed parallel halfword subtract, saturating

Thumb syntax (32-bit, v6T2)

QSUB16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

QSUB16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

QSUB8

Description

Signed parallel byte subtract, saturating

Thumb syntax (32-bit, v6T2)

QSUB8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

QSUB8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

RBIT

Description

Reverse bits

Thumb syntax (32-bit, v6T2)

RBIT

Rd, Rn

[1]

Arm syntax (v6T2)

RBIT

Rd, Rn

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

REV

Description

Reverse byte order

Thumb syntax (16-bit, v6)

REV

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

REV

Rd, Rn

[1]

Arm syntax (v6T2)

REV

Rd, Rn

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

REV16

Description

Reverse halfword byte order

Thumb syntax (16-bit, v6)

REV16

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

REV16

Rd, Rn

[1]

Arm syntax (v6T2)

REV16

Rd, Rn

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

REVSH

Description

Reverse low halfword byte order, sign extend

Thumb syntax (16-bit, v6)

REVSH

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

REVSH

Rd, Rn

[1]

Arm syntax (v6T2)

REVSH

Rd, Rn

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

RFE

Description

Return from exception

Thumb syntax (32-bit, v6)

RFE	SP	[1]
RFE	SP!	[1]

Arm syntax (v6)

RFE	SP	[1]
RFE	SP!	[1]

Notes

[1] Rd ≠ PC

RFEDA

Description

Return from exception, decrement after

Arm syntax (v6)

RFEDA	SP	[1]
RFEDA	SP!	[1]

Notes

[1] Rd ≠ PC

RFEDB

Description

Return from exception, decrement before

Thumb syntax (32-bit, v6)

RFEDB	SP	[1]
RFEDB	SP!	[1]

Arm syntax (v6)

RFEDB	SP	[1]
RFEDB	SP!	[1]

Notes

[1] Rd ≠ PC

RFEIA

Description

Return from exception, increment after

Thumb syntax (32-bit, v6)

RFEIA	SP	[1]
RFEIA	SP!	[1]

Arm syntax (v6)

RFEIA	SP	[1]
RFEIA	SP!	[1]

Notes

[1] Rd ≠ PC

RFEIB

Description

Return from exception, increment before

Arm syntax (v6)

RFEIB	SP	[1]
RFEIB	SP!	[1]

Notes

[1] Rd ≠ PC

ROR

Description

Rotate right

Thumb syntax (16-bit, v4T)

ROR

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

ROR	Rd, Rn, Rm	[2]
ROR	Rd, Rn, #1…31	[3]
RORS	Rd, Rn, Rm	[2]
RORS	Rd, Rn, #1…31	[3]

Arm syntax (v4T)

ROR	Rd, Rn, Rm	[2]
ROR	Rd, Rn, #1…31	[3]
RORS	Rd, Rn, Rm	[2]
RORS	Rd, Rn, #1…31	[3]

Notes

[1] Rd, Rn must be R0…R7
[2] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP
[3] Rd, Rn ≠ PC; Rd, Rn ≠ SP

RRX

Description

Rotate right through carry

Thumb syntax (32-bit, v6T2)

RRX	Rd, Rn	[1]
RRXS	Rd, Rn	[1]

Arm syntax (v4T)

RRX	Rd, Rn	[1]
RRXS	Rd, Rn	[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

RSB

Description

Reverse subtract

Thumb syntax (16-bit, v4T)

RSB

Rd, Rn, #0

[1]

Thumb syntax (32-bit, v6T2)

RSB	Rd, Rn, #const	[2]
RSB	Rd, Rn, Rm, shift	[3]
RSBS	Rd, Rn, #const	[2]
RSBS	Rd, Rn, Rm, shift	[3]

Arm syntax (v4T)

RSB	Rd, Rn, #const	[4]
RSB	Rd, Rn, Rm, shift	[5]
RSBS	Rd, Rn, #const	[4]
RSBS	Rd, Rn, Rm, shift	[5]

Notes

[1] Rd, Rn must be R0…R7
[2] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is $xx ROR 2n
[5] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

RSC

Description

Reverse subtract with carry

Arm syntax (v4T)

RSC	Rd, Rn, #const	[1]
RSC	Rd, Rn, Rm, shift	[2]
RSCS	Rd, Rn, #const	[1]
RSCS	Rd, Rn, Rm, shift	[2]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is $xx ROR 2n
[2] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

SADD16

Thumb syntax (32-bit, v6T2)

SADD16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SADD16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SADD8

Thumb syntax (32-bit, v6T2)

SADD8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SADD8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SASX

Thumb syntax (32-bit, v6T2)

SASX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SASX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SBC

Description

Subtract with carry

Thumb syntax (16-bit, v4T)

SBC

Rd, Rn

[1]

Thumb syntax (32-bit, v6T2)

SBC	Rd, Rn, #const	[2]
SBC	Rd, Rn, Rm, shift	[3]
SBCS	Rd, Rn, #const	[2]
SBCS	Rd, Rn, Rm, shift	[3]

Arm syntax (v4T)

SBC	Rd, Rn, #const	[4]
SBC	Rd, Rn, Rm, shift	[5]
SBCS	Rd, Rn, #const	[4]
SBCS	Rd, Rn, Rm, shift	[5]

Notes

[1] Rd, Rn must be R0…R7
[2] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is $xx ROR 2n
[5] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

SBFX

Description

Signed bitfield extract

Thumb syntax (32-bit, v6T2)

SBFX

Rd, Rn, #lsb, #width

[1]

Arm syntax (v6T2)

SBFX

Rd, Rn, #lsb, #width

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

SDIV

Description

Signed divide

Thumb syntax (32-bit, v7)

SDIV

Rd, Rn, Rm

[1]

Arm syntax (v)

SDIV

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SEL

Thumb syntax (32-bit, v6T2)

SEL

Rd, Rn, Rm

Arm syntax (v6T2)

SEL

Rd, Rn, Rm

SETEND

Description

Set byte order

Thumb syntax (16-bit, v6)

SETEND

endian

[1]

Arm syntax (v6)

SETEND

endian

[1]

Notes

[1] endian is ’LE’ or ’BE’; not permitted in an IT block

SETPAN

Thumb syntax (16-bit, v)

SETPAN

#0…1

[1]

Arm syntax (v)

SETPAN

#0…1

Notes

[1] not permitted in an IT block

SEV

Description

Signal event

Thumb syntax (16-bit, v6K)

SEV

Thumb syntax (32-bit, v7)

SEV

Arm syntax (v6K)

SEV

SEVL

Description

Signal event, local

Thumb syntax (16-bit, v)

SEVL

Thumb syntax (32-bit, v)

SEVL

Arm syntax (v)

SEVL

SHADD16

Thumb syntax (32-bit, v6T2)

SHADD16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SHADD16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SHADD8

Thumb syntax (32-bit, v6T2)

SHADD8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SHADD8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SHASX

Thumb syntax (32-bit, v6T2)

SHASX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SHASX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SHSAX

Thumb syntax (32-bit, v6T2)

SHSAX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SHSAX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SHSUB16

Thumb syntax (32-bit, v6T2)

SHSUB16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SHSUB16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SHSUB8

Thumb syntax (32-bit, v6T2)

SHSUB8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SHSUB8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMC

Description

Secure monitor call

Thumb syntax (32-bit, v)

SMC

#0…15

Arm syntax (v)

SMC

#0…15

SMLABB

Description

Signed halfword multiply, word accumulate

Thumb syntax (32-bit, v6T2)

SMLABB

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLABB

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLABT

Description

Signed halfword multiply, word accumulate

Thumb syntax (32-bit, v6T2)

SMLABT

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLABT

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLAD

Description

Dual 16-bit signed multiply-add

Thumb syntax (32-bit, v6T2)

SMLAD

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLAD

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLADX

Thumb syntax (32-bit, v6T2)

SMLADX

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLADX

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLAL

Thumb syntax (32-bit, v6T2)

SMLAL

Rd, Rn, Rm, Ra

[1]

Arm syntax (v4T)

SMLAL	Rd, Rn, Rm, Ra	[2]
SMLALS	Rd, Rn, Rm, Ra	[2]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn
[2] Rd, Rn, Rm, Ra ≠ PC; Rd ≠ Rn ≠ Rm

SMLALBB

Description

Signed halfword multiply, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLALBB

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLALBB

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn

SMLALBT

Description

Signed halfword multiply, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLALBT

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLALBT

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn

SMLALD

Description

Dual 16-bit signed multiply-add, doubleword accumulate

Thumb syntax (32-bit, v7E-M)

SMLALD

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLALD

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn

SMLALDX

Thumb syntax (32-bit, v7E-M)

SMLALDX

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLALDX

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn

SMLALTB

Description

Signed halfword multiply, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLALTB

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLALTB

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn

SMLALTT

Description

Signed halfword multiply, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLALTT

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLALTT

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn

SMLATB

Description

Signed halfword multiply, word accumulate

Thumb syntax (32-bit, v6T2)

SMLATB

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLATB

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLATT

Description

Signed halfword multiply, word accumulate

Thumb syntax (32-bit, v6T2)

SMLATT

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLATT

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLAWB

Description

Signed multiply-accumulate wide

Thumb syntax (32-bit, v6T2)

SMLAWB

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLAWB

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLAWT

Description

Signed multiply-accumulate wide

Thumb syntax (32-bit, v6T2)

SMLAWT

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLAWT

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLSD

Description

Dual 16-bit signed multiply-subtract

Thumb syntax (32-bit, v6T2)

SMLSD

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLSD

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLSDX

Thumb syntax (32-bit, v6T2)

SMLSDX

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLSDX

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMLSLD

Description

Dual 16-bit signed multiply-subtract, doubleword accumulate

Thumb syntax (32-bit, v6T2)

SMLSLD

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLSLD

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn

SMLSLDX

Thumb syntax (32-bit, v6T2)

SMLSLDX

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMLSLDX

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn

SMMLA

Thumb syntax (32-bit, v6T2)

SMMLA

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMMLA

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMMLAR

Thumb syntax (32-bit, v6T2)

SMMLAR

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMMLAR

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMMLS

Thumb syntax (32-bit, v6T2)

SMMLS

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMMLS

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMMLSR

Thumb syntax (32-bit, v6T2)

SMMLSR

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

SMMLSR

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

SMMUL

Thumb syntax (32-bit, v6T2)

SMMUL

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SMMUL

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMMULR

Thumb syntax (32-bit, v6T2)

SMMULR

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SMMULR

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMUAD

Thumb syntax (32-bit, v6T2)

SMUAD

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SMUAD

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMUADX

Thumb syntax (32-bit, v6T2)

SMUADX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SMUADX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMULBB

Description

Signed halfword multiply

Thumb syntax (32-bit, v6T2)

SMULBB

Rd, Rn, Rm

[1]

Arm syntax (v)

SMULBB

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMULBT

Description

Signed halfword multiply

Thumb syntax (32-bit, v6T2)

SMULBT

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SMULBT

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMULL

Thumb syntax (32-bit, v6T2)

SMULL

Rd, Rn, Rm, Ra

[1]

Arm syntax (v4T)

SMULL	Rd, Rn, Rm, Ra	[2]
SMULLS	Rd, Rn, Rm, Ra	[2]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn
[2] Rd, Rn, Rm, Ra ≠ PC; Rd ≠ Rn ≠ Rm

SMULTB

Description

Signed halfword multiply

Thumb syntax (32-bit, v6T2)

SMULTB

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SMULTB

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMULTT

Description

Signed halfword multiply

Thumb syntax (32-bit, v6T2)

SMULTT

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SMULTT

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMULWB

Description

Signed multiply wide

Thumb syntax (32-bit, v6T2)

SMULWB

Rd, Rn, Rm

[1]

Arm syntax (v)

SMULWB

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMULWT

Description

Signed multiply wide

Thumb syntax (32-bit, v6T2)

SMULWT

Rd, Rn, Rm

[1]

Arm syntax (v)

SMULWT

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMUSD

Thumb syntax (32-bit, v6T2)

SMUSD

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SMUSD

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SMUSDX

Thumb syntax (32-bit, v6T2)

SMUSDX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SMUSDX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SRS

Description

Store return state

Thumb syntax (32-bit, v6)

SRS	SP, #0…31
SRS	SP!, #0…31

Arm syntax (v6)

SRS	SP, #0…31
SRS	SP!, #0…31

SRSDA

Description

Store return state, decrement after

Arm syntax (v6)

SRSDA	SP, #0…31
SRSDA	SP!, #0…31

SRSDB

Description

Store return state, decrement before

Thumb syntax (32-bit, v6)

SRSDB	SP, #0…31
SRSDB	SP!, #0…31

Arm syntax (v6)

SRSDB	SP, #0…31
SRSDB	SP!, #0…31

SRSIA

Description

Store return state, increment after

Thumb syntax (32-bit, v6)

SRSIA	SP, #0…31
SRSIA	SP!, #0…31

Arm syntax (v6)

SRSIA	SP, #0…31
SRSIA	SP!, #0…31

SRSIB

Description

Store return state, increment before

Arm syntax (v6)

SRSIB	SP, #0…31
SRSIB	SP!, #0…31

SSAT

Description

Signed saturate

Thumb syntax (32-bit, v6T2)

SSAT

Rd, #1…32, Rn

[1]

Arm syntax (v6T2)

SSAT

Rd, #1…32, Rn

[1]

Notes

[1] Rd, Rm ≠ PC; Rd, Rm ≠ SP

SSAT16

Description

Signed saturate, parallel halfwords

Thumb syntax (32-bit, v6T2)

SSAT16

Rd, #1…16, Rn

[1]

Arm syntax (v6T2)

SSAT16

Rd, #1…16, Rn

[1]

Notes

[1] Rd, Rm ≠ PC; Rd, Rm ≠ SP

SSAX

Thumb syntax (32-bit, v6T2)

SSAX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SSAX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SSUB16

Thumb syntax (32-bit, v6T2)

SSUB16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SSUB16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SSUB8

Thumb syntax (32-bit, v6T2)

SSUB8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

SSUB8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

STL

Description

Store-release word

Thumb syntax (32-bit, v)

STL

Rd, [Rn]

[1]

Arm syntax (v)

STL

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

STLB

Description

Store-release byte

Thumb syntax (32-bit, v)

STLB

Rd, [Rn]

[1]

Arm syntax (v)

STLB

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

STLH

Description

Store-release halfword

Thumb syntax (32-bit, v)

STLH

Rd, [Rn]

[1]

Arm syntax (v)

STLH

Rd, [Rn]

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

STM

Description

Store multiple

Thumb syntax (16-bit, v4T)

STM	Rd, {Rn, Rm…}
STM	Rd!, {Rn, Rm…}	[1]

Thumb syntax (32-bit, v6T2)

STM	Rd, {Rn, Rm…}	[2]
STM	Rd!, {Rn, Rm…}	[2]

Arm syntax (v4T)

STM	Rd, {Rn, Rm…}	[2]
STM	Rd!, {Rn, Rm…}	[2]

Notes

[1] Rd must be R0…R7; Rd ≠ PC
[2] Rd ≠ PC

STMDA

Description

Store multiple decrement after

Thumb syntax (16-bit, v4T)

STMDA

Rd, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

STMDA	Rd, {Rn, Rm…}	[1]
STMDA	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

STMDA	Rd, {Rn, Rm…}	[1]
STMDA	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

STMDB

Description

Store multiple decrement before

Thumb syntax (16-bit, v4T)

STMDB

SP!, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

STMDB	Rd, {Rn, Rm…}	[1]
STMDB	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

STMDB	Rd, {Rn, Rm…}	[1]
STMDB	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

STMEA

Description

Store multiple empty ascending

Thumb syntax (16-bit, v4T)

STMEA

SP!, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

STMEA	Rd, {Rn, Rm…}	[1]
STMEA	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

STMEA	Rd, {Rn, Rm…}	[1]
STMEA	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

STMED

Description

Store multiple empty descending

Thumb syntax (16-bit, v4T)

STMED

Rd, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

STMED	Rd, {Rn, Rm…}	[1]
STMED	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

STMED	Rd, {Rn, Rm…}	[1]
STMED	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

STMFA

Description

Store multiple full ascending

Thumb syntax (16-bit, v4T)

STMFA

Rd, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

STMFA	Rd, {Rn, Rm…}	[1]
STMFA	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

STMFA	Rd, {Rn, Rm…}	[1]
STMFA	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

STMFD

Description

Store multiple full descending

Thumb syntax (16-bit, v4T)

STMFD	Rd, {Rn, Rm…}
STMFD	Rd!, {Rn, Rm…}	[1]

Thumb syntax (32-bit, v6T2)

STMFD	Rd, {Rn, Rm…}	[2]
STMFD	Rd!, {Rn, Rm…}	[2]

Arm syntax (v4T)

STMFD	Rd, {Rn, Rm…}	[2]
STMFD	Rd!, {Rn, Rm…}	[2]

Notes

[1] Rd must be R0…R7; Rd ≠ PC
[2] Rd ≠ PC

STMIA

Description

Store multiple increment after

Thumb syntax (16-bit, v4T)

STMIA	Rd, {Rn, Rm…}
STMIA	Rd!, {Rn, Rm…}	[1]

Thumb syntax (32-bit, v6T2)

STMIA	Rd, {Rn, Rm…}	[2]
STMIA	Rd!, {Rn, Rm…}	[2]

Arm syntax (v4T)

STMIA	Rd, {Rn, Rm…}	[2]
STMIA	Rd!, {Rn, Rm…}	[2]

Notes

[1] Rd must be R0…R7; Rd ≠ PC
[2] Rd ≠ PC

STMIB

Description

Store multiple increment before

Thumb syntax (16-bit, v4T)

STMIB

Rd, {Rn, Rm…}

Thumb syntax (32-bit, v6T2)

STMIB	Rd, {Rn, Rm…}	[1]
STMIB	Rd!, {Rn, Rm…}	[1]

Arm syntax (v4T)

STMIB	Rd, {Rn, Rm…}	[1]
STMIB	Rd!, {Rn, Rm…}	[1]

Notes

[1] Rd ≠ PC

STR

Description

Store word

Thumb syntax (16-bit, v4T)

STR	Rt, [Rn, #0…124]	[1]
STR	Rt, [SP, #0…1020]	[2]
STR	Rt, [Rn, Rm]	[3]

Thumb syntax (32-bit, v6T2)

STR	Rt, [Rn, #−255…4095]	[4]
STR	Rt, [Rn, #−255…255]!	[5]
STR	Rt, [Rn], #−255…255	[5]
STR	Rt, [Rn, Rm, LSL #1…3]	[6]

Arm syntax (v4T)

STR	Rt, [Rn, #−4095…4095]	[5]
STR	Rt, [Rn, #−4095…4095]!	[5]
STR	Rt, [Rn], #−4095…4095	[5]
STR	Rt, [Rn], ±Rm, shift	[7]
STR	Rt, [Rn, ±Rm]	[7]
STR	Rt, [Rn, ±Rm]!	[7]

Notes

[1] Rt, Rn must be R0…R7; offset a multiple of 4
[2] offset a multiple of 4
[3] Rt, Rn, Rm must be R0…R7
[4] Rt, Rn ≠ PC
[5] Rt, Rn ≠ PC; Rt ≠ Rn
[6] Rt, Rn, Rm ≠ PC; Rm ≠ SP; LSL #0 is also permitted
[7] Rt, Rn, Rm ≠ PC; Rm ≠ SP; Rt ≠ Rn

STRB

Description

Store byte

Thumb syntax (16-bit, v4T)

STRB	Rt, [Rn, #0…31]	[1]
STRB	Rt, [Rn, Rm]	[2]

Thumb syntax (32-bit, v6T2)

STRB	Rt, [Rn, #−255…4095]	[3]
STRB	Rt, [Rn, #−255…255]!	[4]
STRB	Rt, [Rn], #−255…255	[4]
STRB	Rt, [Rn, Rm, LSL #1…3]	[5]

Arm syntax (v4T)

STRB	Rt, [Rn, #−4095…4095]	[3]
STRB	Rt, [Rn, #−4095…4095]!	[4]
STRB	Rt, [Rn], #−4095…4095	[4]
STRB	Rt, [Rn], ±Rm, shift	[6]
STRB	Rt, [Rn, ±Rm]	[7]
STRB	Rt, [Rn, ±Rm]!	[6]

Notes

[1] Rt, Rn must be R0…R7
[2] Rt, Rn, Rm must be R0…R7
[3] Rt, Rn ≠ PC; Rt ≠ SP
[4] Rt, Rn ≠ PC; Rt ≠ SP; Rt ≠ Rn
[5] Rt, Rn, Rm ≠ PC; Rt, Rm ≠ SP; LSL #0 is also permitted
[6] Rt, Rn, Rm ≠ PC; Rt, Rm ≠ SP; Rt ≠ Rn
[7] Rt, Rn, Rm ≠ PC; Rt, Rm ≠ SP

STRBT

Description

Store byte, user mode

Thumb syntax (32-bit, v6T2)

STRBT

Rt, [Rn, #0…255]

[1]

Arm syntax (v4T)

STRBT	Rt, [Rn], #−4095…4095	[2]
STRBT	Rt, [Rn], ±Rm, shift	[3]

Notes

[1] Rt, Rn ≠ PC; Rt ≠ SP
[2] Rt, Rn ≠ PC; Rt ≠ SP; Rt ≠ Rn
[3] Rt, Rn, Rm ≠ PC; Rt, Rm ≠ SP; Rt ≠ Rn

STRD

Description

Store doubleword

Thumb syntax (32-bit, v6T2)

STRD	Rd1, Rd2, [Rn, #−1020…1020]	[1]
STRD	Rd1, Rd2, [Rn, #−1020…1020]!	[2]
STRD	Rd1, Rd2, [Rn], #−1020…1020	[2]

Arm syntax (v)

STRD	Rd1, Rd2, [Rn, #−255…255]	[3]
STRD	Rd1, Rd2, [Rn, #−255…255]!	[4]
STRD	Rd1, Rd2, [Rn], #−255…255	[3]
STRD	Rd1, Rd2, [Rn, ±Rm]	[5]
STRD	Rd1, Rd2, [Rn, ±Rm]!	[6]
STRD	Rd1, Rd2, [Rn], ±Rm	[6]

Notes

[1] Rd1, Rd2, Rn ≠ PC; Rd1, Rd2 ≠ SP; offset a multiple of 4
[2] Rd1, Rd2, Rn ≠ PC; Rd1, Rd2 ≠ SP; Rd1 ≠ Rn; Rd2 ≠ Rn; offset a multiple of 4
[3] Rd1, Rd2, Rn ≠ PC; Rd2 ≠ SP; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register
[4] Rd1, Rd2, Rn ≠ PC; Rd2 ≠ SP; Rd1 ≠ Rn; Rd2 ≠ Rn; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register
[5] Rd1, Rd2, Rn, Rm ≠ PC; Rd2, Rm ≠ SP; Rd1 ≠ Rd2; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register
[6] Rd1, Rd2, Rn, Rm ≠ PC; Rd2, Rm ≠ SP; Rd1 ≠ Rd2 ≠ Rm; Rd1 must be an even−numbered register; Rd2 must be the following odd−numbered register

STREX

Description

Store word exclusive

Thumb syntax (32-bit, v6T2)

STREX

Rd1, Rd2, [Rn, #0…1020]

[1]

Arm syntax (v6T2)

STREX

Rd1, Rd2, [Rn]

[2]

Notes

[1] Rd1, Rd2, Rn ≠ PC; Rd1, Rd2 ≠ SP; Rd1 ≠ Rd2; Rd1 ≠ Rn; offset a multiple of 4
[2] Rd1, Rd2, Rn ≠ PC; Rd1, Rd2 ≠ SP; Rd1 ≠ Rd2; Rd1 ≠ Rn

STREXB

Description

Store byte exclusive

Thumb syntax (32-bit, v6T2)

STREXB

Rd1, Rd2, [Rn]

[1]

Arm syntax (v6T2)

STREXB

Rd1, Rd2, [Rn]

[1]

Notes

[1] Rd1, Rd2, Rn ≠ PC; Rd1, Rd2 ≠ SP; Rd1 ≠ Rd2; Rd1 ≠ Rn

STREXD

Description

Store doubleword exclusive

Thumb syntax (32-bit, v6T2)

STREXD

Rd, Rt1, Rt2, [Rn]

[1]

Arm syntax (v6T2)

STREXD

Rd, Rt1, Rt2, [Rn]

[2]

Notes

[1] Rd, Rt1, Rt2, Rn ≠ PC; Rd, Rt1, Rt2 ≠ SP; Rd ≠ Rt1; Rd ≠ Rt2; Rd ≠ Rn
[2] Rd, Rt1, Rt2, Rn ≠ PC; Rd, Rt1, Rt2 ≠ SP; Rd ≠ Rt1; Rd ≠ Rt2; Rd ≠ Rn; Rd must be an even−numbered register; Rt1 must be the following odd−numbered register

STREXH

Description

Store halfword exclusive

Thumb syntax (32-bit, v6T2)

STREXH

Rd1, Rd2, [Rn]

[1]

Arm syntax (v6T2)

STREXH

Rd1, Rd2, [Rn]

[1]

Notes

[1] Rd1, Rd2, Rn ≠ PC; Rd1, Rd2 ≠ SP; Rd1 ≠ Rd2; Rd1 ≠ Rn

STRH

Description

Store halfword

Thumb syntax (16-bit, v4T)

STRH	Rt, [Rn, #0…62]	[1]
STRH	Rt, [Rn, Rm]	[2]

Thumb syntax (32-bit, v6T2)

STRH	Rt, [Rn, #−255…4095]	[3]
STRH	Rt, [Rn, #−255…255]!	[4]
STRH	Rt, [Rn], #−255…255	[4]
STRH	Rt, [Rn, Rm, LSL #1…3]	[5]

Arm syntax (v4T)

STRH	Rt, [Rn, #−255…255]	[3]
STRH	Rt, [Rn, #−255…255]!	[4]
STRH	Rt, [Rn], #−255…255	[4]
STRH	Rt, [Rn, ±Rm]	[6]
STRH	Rt, [Rn, ±Rm]!	[7]
STRH	Rt, [Rn], ±Rm	[7]

Notes

[1] Rt, Rn must be R0…R7; offset a multiple of 2
[2] Rt, Rn, Rm must be R0…R7
[3] Rt, Rn ≠ PC; Rt ≠ SP
[4] Rt, Rn ≠ PC; Rt ≠ SP; Rt ≠ Rn
[5] Rt, Rn, Rm ≠ PC; Rt, Rm ≠ SP; LSL #0 is also permitted
[6] Rt, Rn, Rm ≠ PC; Rt, Rm ≠ SP
[7] Rt, Rn, Rm ≠ PC; Rt, Rm ≠ SP; Rt ≠ Rn

STRHT

Description

Store halfword, user mode

Thumb syntax (32-bit, v6T2)

STRHT

Rt, [Rn, #0…255]

[1]

Arm syntax (v6T2)

STRHT	Rt, [Rn], #−255…255	[2]
STRHT	Rt, [Rn], ±Rm	[3]

Notes

[1] Rt, Rn ≠ PC; Rt ≠ SP
[2] Rt, Rn ≠ PC; Rt ≠ SP; Rt ≠ Rn
[3] Rt, Rn, Rm ≠ PC; Rt, Rm ≠ SP; Rt ≠ Rn

STRT

Description

Store word, user mode

Thumb syntax (32-bit, v6T2)

STRT

Rt, [Rn, #0…255]

[1]

Arm syntax (v4T)

STRT	Rt, [Rn], #−4095…4095	[2]
STRT	Rt, [Rn], ±Rm, shift	[3]

Notes

[1] Rt, Rn ≠ PC; Rt ≠ SP
[2] Rt, Rn ≠ PC; Rt ≠ SP; Rt ≠ Rn
[3] Rt, Rn, Rm ≠ PC; Rt, Rm ≠ SP; Rt ≠ Rn

SUB

Description

Subtract

Thumb syntax (16-bit, v4T)

SUB	Rd, Rn, Rm	[1]
SUB	Rd, #0…255	[2]
SUB	Rd, Rn, #0…7	[3]
SUB	SP, SP, #0…508	[4]
SUB	Rd, SP, #0	[2]
SUB	Rd, PC, #0	[2]

Thumb syntax (32-bit, v6T2)

SUB	Rd, Rn, #0…4095	[5]
SUB	Rd, Rn, #const	[6]
SUB	Rd, Rn, Rm, shift	[7]
SUBS	Rd, Rn, #const	[6]
SUBS	Rd, Rn, Rm, shift	[7]

Arm syntax (v4T)

SUB	Rd, Rn, #const	[8]
SUB	Rd, Rn, Rm, shift	[9]
SUB	Rd, SP, Rm, shift	[10]
SUBS	Rd, Rn, #const	[11]
SUBS	Rd, Rn, Rm, shift	[9]
SUBS	Rd, SP, Rm, shift	[10]

Notes

[1] Rd, Rn, Rm must be R0…R7
[2] Rd must be R0…R7
[3] Rd, Rn must be R0…R7
[4] offset a multiple of 4
[5] Rd ≠ PC; Rd ≠ SP
[6] Rd, Rn ≠ PC; Rd, Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[7] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[8] Rd ≠ SP; const is $xx ROR 2n
[9] Rd, Rn, Rm ≠ PC; Rd, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX
[10] Rd, Rm ≠ PC; Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX
[11] Rd ≠ PC; Rd ≠ SP; const is $xx ROR 2n

SUBW

Description

Subtract

Thumb syntax (32-bit, v6T2)

SUBW

Rd, Rn, #0…4095

[1]

Notes

[1] Rd ≠ PC; Rd ≠ SP

SVC

Description

Supervisor call

Thumb syntax (16-bit, v4T)

SVC

#0…255

Arm syntax (v4T)

SVC

0…16777215

SXTAB

Description

Sign-extend byte, accumulate

Thumb syntax (32-bit, v6T2)

SXTAB

Rd, Rn, Rm{, ROR #imm}

[1]

Arm syntax (v6T2)

SXTAB

Rd, Rn, Rm{, ROR #imm}

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SXTAB16

Thumb syntax (32-bit, v6T2)

SXTAB16

Rd, Rn, Rm{, ROR #imm}

[1]

Arm syntax (v6T2)

SXTAB16

Rd, Rn, Rm{, ROR #imm}

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SXTAH

Description

Sign-extend halfword, accumulate

Thumb syntax (32-bit, v6T2)

SXTAH

Rd, Rn, Rm{, ROR #imm}

[1]

Arm syntax (v6T2)

SXTAH

Rd, Rn, Rm{, ROR #imm}

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

SXTB

Description

Sign extend byte

Thumb syntax (16-bit, v6)

SXTB

Rd, Rn

Thumb syntax (32-bit, v6T2)

SXTB

Rd, Rn{, ROR #imm}

[1]

Arm syntax (v6T2)

SXTB

Rd, Rn{, ROR #imm}

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

SXTB16

Thumb syntax (32-bit, v6T2)

SXTB16

Rd, Rn{, ROR #imm}

[1]

Arm syntax (v6T2)

SXTB16

Rd, Rn{, ROR #imm}

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

SXTH

Description

Sign extend halfword

Thumb syntax (16-bit, v6)

SXTH

Rd, Rn

Thumb syntax (32-bit, v6T2)

SXTH

Rd, Rn{, ROR #imm}

[1]

Arm syntax (v6T2)

SXTH

Rd, Rn{, ROR #imm}

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

TBB

Description

Table branch, byte

Thumb syntax (32-bit, v6T2)

TBB

[Rd, Rn]

TBH

Description

Table branch, halfword

Thumb syntax (32-bit, v6T2)

TBH

[Rd, Rn, LSL #1]

TEQ

Description

Test equivalence

Thumb syntax (32-bit, v6T2)

TEQ	Rn, #const	[1]
TEQ	Rn, Rm, shift	[2]

Arm syntax (v4T)

TEQ	Rn, #const	[3]
TEQ	Rn, Rm, shift	[4]

Notes

[1] Rn ≠ PC; Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[2] Rn, Rm ≠ PC; Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[3] Rn ≠ PC; Rn ≠ SP; const is $xx ROR 2n
[4] Rn, Rm ≠ PC; Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

TST

Description

Test

Thumb syntax (16-bit, v4T)

TST

Rn, Rm

[1]

Thumb syntax (32-bit, v6T2)

TST	Rn, #const	[2]
TST	Rn, Rm, shift	[3]

Arm syntax (v4T)

TST	Rn, #const	[4]
TST	Rn, Rm, shift	[5]

Notes

[1] Rn, Rm must be R0…R7
[2] Rn ≠ PC; Rn ≠ SP; const is one of $00xx00xx, $xx00xx00, $xxxxxxxx, $xx LSL 0…24
[3] Rn, Rm ≠ PC; Rn, Rm ≠ SP; shift is one of LSL #0…31, LSR #1…32, ASR #1…32, RRX
[4] Rn ≠ PC; Rn ≠ SP; const is $xx ROR 2n
[5] Rn, Rm ≠ PC; Rn, Rm ≠ SP; shift is one of LSL #0…31/Rs, LSR #1…32/Rs, ASR #1…32/Rs, ROR #1…31/Rs, RRX

TT

Description

Test target

Thumb syntax (32-bit, v8-M.BASE)

TT

Rd, Rn

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

TTA

Description

Test target

Thumb syntax (32-bit, v8-M.BASE)

TTA

Rd, Rn

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

TTAT

Description

Test target

Thumb syntax (32-bit, v8-M.BASE)

TTAT

Rd, Rn

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

TTT

Description

Test target

Thumb syntax (32-bit, v8-M.BASE)

TTT

Rd, Rn

[1]

Notes

[1] Rd, Rn ≠ PC; Rd ≠ SP

UADD16

Thumb syntax (32-bit, v6T2)

UADD16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UADD16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UADD8

Description

Unsigned parallel byte add

Thumb syntax (32-bit, v6T2)

UADD8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UADD8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UASX

Thumb syntax (32-bit, v6T2)

UASX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UASX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UBFX

Description

Unsigned bitfield extract

Thumb syntax (32-bit, v6T2)

UBFX

Rd, Rn, #lsb, #width

[1]

Arm syntax (v6T2)

UBFX

Rd, Rn, #lsb, #width

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

UDF

Description

Undefined

Thumb syntax (16-bit, v4T)

UDF

#0…255

Thumb syntax (32-bit, v6T2)

UDF

#0…65535

Arm syntax (v4T)

UDF

Rd, #0…65535

UDIV

Description

Unsigned divide

Thumb syntax (32-bit, v7)

UDIV

Rd, Rn, Rm

[1]

Arm syntax (v)

UDIV

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UHADD16

Thumb syntax (32-bit, v6T2)

UHADD16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UHADD16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UHADD8

Thumb syntax (32-bit, v6T2)

UHADD8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UHADD8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UHASX

Thumb syntax (32-bit, v6T2)

UHASX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UHASX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UHSAX

Thumb syntax (32-bit, v6T2)

UHSAX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UHSAX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UHSUB16

Thumb syntax (32-bit, v6T2)

UHSUB16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UHSUB16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UHSUB8

Thumb syntax (32-bit, v6T2)

UHSUB8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UHSUB8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UMAAL

Thumb syntax (32-bit, v6T2)

UMAAL

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

UMAAL

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn

UMLAL

Thumb syntax (32-bit, v6T2)

UMLAL

Rd, Rn, Rm, Ra

[1]

Arm syntax (v4T)

UMLAL	Rd, Rn, Rm, Ra	[2]
UMLALS	Rd, Rn, Rm, Ra	[2]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn
[2] Rd, Rn, Rm, Ra ≠ PC; Rd ≠ Rn ≠ Rm

UMULL

Thumb syntax (32-bit, v6T2)

UMULL

Rd, Rn, Rm, Ra

[1]

Arm syntax (v4T)

UMULL	Rd, Rn, Rm, Ra	[2]
UMULLS	Rd, Rn, Rm, Ra	[2]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP; Rd ≠ Rn
[2] Rd, Rn, Rm, Ra ≠ PC; Rd ≠ Rn ≠ Rm

UQADD16

Description

Unsigned parallel halfword add, saturating

Thumb syntax (32-bit, v6T2)

UQADD16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UQADD16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UQADD8

Description

Unsigned parallel byte add, saturating

Thumb syntax (32-bit, v6T2)

UQADD8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UQADD8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UQASX

Thumb syntax (32-bit, v6T2)

UQASX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UQASX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UQSAX

Thumb syntax (32-bit, v6T2)

UQSAX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UQSAX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UQSUB16

Description

unsigned parallel halfword subtract, saturating

Thumb syntax (32-bit, v6T2)

UQSUB16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UQSUB16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UQSUB8

Description

unsigned parallel byte subtract, saturating

Thumb syntax (32-bit, v6T2)

UQSUB8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

UQSUB8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

USAD8

Thumb syntax (32-bit, v6T2)

USAD8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

USAD8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

USADA8

Thumb syntax (32-bit, v6T2)

USADA8

Rd, Rn, Rm, Ra

[1]

Arm syntax (v6T2)

USADA8

Rd, Rn, Rm, Ra

[1]

Notes

[1] Rd, Rn, Rm, Ra ≠ PC; Rd, Rn, Rm, Ra ≠ SP

USAT

Description

Unsigned saturate

Thumb syntax (32-bit, v6T2)

USAT

Rd, #0…31, Rn

[1]

Arm syntax (v6T2)

USAT

Rd, #0…31, Rn

[1]

Notes

[1] Rd, Rm ≠ PC; Rd, Rm ≠ SP

USAT16

Description

Unsigned saturate, parallel halfwords

Thumb syntax (32-bit, v6T2)

USAT16

Rd, #0…15, Rn

[1]

Arm syntax (v6T2)

USAT16

Rd, #0…15, Rn

[1]

Notes

[1] Rd, Rm ≠ PC; Rd, Rm ≠ SP

USAX

Thumb syntax (32-bit, v6T2)

USAX

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

USAX

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

USUB16

Thumb syntax (32-bit, v6T2)

USUB16

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

USUB16

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

USUB8

Description

unsigned parallel byte subtract

Thumb syntax (32-bit, v6T2)

USUB8

Rd, Rn, Rm

[1]

Arm syntax (v6T2)

USUB8

Rd, Rn, Rm

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UXTAB

Description

Zero-extend byte, accumulate

Thumb syntax (32-bit, v6T2)

UXTAB

Rd, Rn, Rm{, ROR #imm}

[1]

Arm syntax (v6T2)

UXTAB

Rd, Rn, Rm{, ROR #imm}

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UXTAB16

Thumb syntax (32-bit, v6T2)

UXTAB16

Rd, Rn, Rm{, ROR #imm}

[1]

Arm syntax (v6T2)

UXTAB16

Rd, Rn, Rm{, ROR #imm}

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UXTAH

Description

Zero-extend halfword, accumulate

Thumb syntax (32-bit, v6T2)

UXTAH

Rd, Rn, Rm{, ROR #imm}

[1]

Arm syntax (v6T2)

UXTAH

Rd, Rn, Rm{, ROR #imm}

[1]

Notes

[1] Rd, Rn, Rm ≠ PC; Rd, Rn, Rm ≠ SP

UXTB

Description

Zero extend byte

Thumb syntax (16-bit, v6)

UXTB

Rd, Rn

Thumb syntax (32-bit, v6T2)

UXTB

Rd, Rn{, ROR #imm}

[1]

Arm syntax (v6T2)

UXTB

Rd, Rn{, ROR #imm}

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

UXTB16

Thumb syntax (32-bit, v6T2)

UXTB16

Rd, Rn{, ROR #imm}

[1]

Arm syntax (v6T2)

UXTB16

Rd, Rn{, ROR #imm}

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

UXTH

Description

Zero extend halfword

Thumb syntax (16-bit, v6)

UXTH

Rd, Rn

Thumb syntax (32-bit, v6T2)

UXTH

Rd, Rn{, ROR #imm}

[1]

Arm syntax (v6T2)

UXTH

Rd, Rn{, ROR #imm}

[1]

Notes

[1] Rd, Rn ≠ PC; Rd, Rn ≠ SP

VABS

Description

Floating-point absolute

Thumb syntax (32-bit, v7)

VABS.F32	Sd, Sn
VABS.F64	Dd, Dn

VADD

Description

Floating-point add

Thumb syntax (32-bit, v7)

VADD.F32	Sd, Sn, Sm
VADD.F64	Dd, Dn, Dm

VCMP

Description

Floating-point compare

Thumb syntax (32-bit, v7)

VCMP.F32	Sd, Sn
VCMP.F64	Dd, Dn

VCMPE

Description

Floating-point compare raising exception on NaN

Thumb syntax (32-bit, v7)

VCMPE.F32	Sd, Sn
VCMPE.F64	Dd, Dn

VCVT

Description

Floating-point convert

Thumb syntax (32-bit, v7)

VCVT.U32.F32	Sd, Sn
VCVT.S32.F32	Sd, Sn
VCVT.F32.U32	Sd, Sn
VCVT.F32.S32	Sd, Sn
VCVT.F32.F64	Sd, Dn
VCVT.U32.F64	Sd, Dn
VCVT.S32.F64	Sd, Dn
VCVT.F64.F32	Dd, Sn
VCVT.F64.U32	Dd, Sn
VCVT.F64.S32	Dd, Sn

VCVTA

Description

Floating-point convert to integer with rounding to nearest with ties away

Thumb syntax (32-bit, v7)

VCVTA.U32.F32	Sd, Sn
VCVTA.S32.F32	Sd, Sn
VCVTA.U32.F64	Sd, Dn
VCVTA.S32.F64	Sd, Dn

VCVTB

Description

Floating-point convert bottom

Thumb syntax (32-bit, v7)

VCVTB.F32.F16	Sd, Sn
VCVTB.F16.F32	Sd, Sn
VCVTB.F16.F64	Sd, Dn
VCVTB.F64.F16	Dd, Sn

VCVTM

Description

Floating-point convert to integer with rounding to minus infinity

Thumb syntax (32-bit, v7)

VCVTM.U32.F32	Sd, Sn
VCVTM.S32.F32	Sd, Sn
VCVTM.U32.F64	Sd, Dn
VCVTM.S32.F64	Sd, Dn

VCVTN

Description

Floating-point convert to integer with rounding to nearest

Thumb syntax (32-bit, v7)

VCVTN.U32.F32	Sd, Sn
VCVTN.S32.F32	Sd, Sn
VCVTN.U32.F64	Sd, Dn
VCVTN.S32.F64	Sd, Dn

VCVTP

Description

Floating-point convert to integer with rounding to positive infinity

Thumb syntax (32-bit, v7)

VCVTP.U32.F32	Sd, Sn
VCVTP.S32.F32	Sd, Sn
VCVTP.U32.F64	Sd, Dn
VCVTP.S32.F64	Sd, Dn

VCVTR

Description

Floating-point convert to integer with rounding from FPSCR

Thumb syntax (32-bit, v7)

VCVTR.U32.F32	Sd, Sn
VCVTR.S32.F32	Sd, Sn
VCVTR.U32.F64	Sd, Dn
VCVTR.S32.F64	Sd, Dn

VCVTT

Thumb syntax (32-bit, v7)

VCVTT.F32.F16	Sd, Sn
VCVTT.F16.F32	Sd, Sn
VCVTT.F16.F64	Sd, Dn
VCVTT.F64.F16	Dd, Sn

VDIV

Description

Floating-point divide

Thumb syntax (32-bit, v7)

VDIV.F32	Sd, Sn, Sm
VDIV.F64	Dd, Dn, Dm

VFMA

Description

Floating-point fused multiply-accumulate

Thumb syntax (32-bit, v7)

VFMA.F32	Sd, Sn, Sm
VFMA.F64	Dd, Dn, Dm

VFMS

Description

Floating-point fused multiply-subtract

Thumb syntax (32-bit, v7)

VFMS.F32	Sd, Sn, Sm
VFMS.F64	Dd, Dn, Dm

VFNMA

Description

Floating-point fused negate-multiply-accumulate

Thumb syntax (32-bit, v7)

VFNMA.F32	Sd, Sn, Sm
VFNMA.F64	Dd, Dn, Dm

VFNMS

Description

Floating-point fused negate-multiply-subtract

Thumb syntax (32-bit, v7)

VFNMS.F32	Sd, Sn, Sm
VFNMS.F64	Dd, Dn, Dm

VLDR

Description

Floating-point load

Thumb syntax (32-bit, v7)

VLDR.32	Sn, [Rn, #−1020…1020]	[1]
VLDR.64	Dn, [Rn, #−1020…1020]	[1]

Notes

[1] offset a multiple of 4

VMAXNM

Description

Floating-point maximum

Thumb syntax (32-bit, v7)

VMAXNM.F32	Sd, Sn, Sm
VMAXNM.F64	Dd, Dn, Dm

VMINNM

Description

Floating-point minimum

Thumb syntax (32-bit, v7)

VMINNM.F32	Sd, Sn, Sm
VMINNM.F64	Dd, Dn, Dm

VMLA

Description

Floating-point multiply-accumulate

Thumb syntax (32-bit, v7)

VMLA.F32	Sd, Sn, Sm
VMLA.F64	Dd, Dn, Dm

VMLS

Description

Floating-point multiply-subtract

Thumb syntax (32-bit, v7)

VMLS.F32	Sd, Sn, Sm
VMLS.F64	Dd, Dn, Dm

VMUL

Description

Floating-point multiply

Thumb syntax (32-bit, v7)

VMUL.F32	Sd, Sn, Sm
VMUL.F64	Dd, Dn, Dm

VNEG

Description

Floating-point negate

Thumb syntax (32-bit, v7)

VNEG.F32	Sd, Sn
VNEG.F64	Dd, Dn

VNMLA

Description

Floating-point negate-multiply-accumulate

Thumb syntax (32-bit, v7)

VNMLA.F32	Sd, Sn, Sm
VNMLA.F64	Dd, Dn, Dm

VNMLS

Description

Floating-point negate-multiply-subtract

Thumb syntax (32-bit, v7)

VNMLS.F32	Sd, Sn, Sm
VNMLS.F64	Dd, Dn, Dm

VNMUL

Description

Floating-point negate-multiply

Thumb syntax (32-bit, v7)

VNMUL.F32	Sd, Sn, Sm
VNMUL.F64	Dd, Dn, Dm

VRINTA

Description

Floating-point round to integer with ties away

Thumb syntax (32-bit, v7)

VRINTA.F32.F32	Sd, Sn
VRINTA.F64.F64	Dd, Dn

VRINTM

Description

Floating-point round to integer towards minus infinity

Thumb syntax (32-bit, v7)

VRINTM.F32.F32	Sd, Sn
VRINTM.F64.F64	Dd, Dn

VRINTN

Description

Floating-point round to integer with ties to even

Thumb syntax (32-bit, v7)

VRINTN.F32.F32	Sd, Sn
VRINTN.F64.F64	Dd, Dn

VRINTP

Description

Floating-point round to integer towards positive infinity

Thumb syntax (32-bit, v7)

VRINTP.F32.F32	Sd, Sn
VRINTP.F64.F64	Dd, Dn

VRINTR

Description

Floating-point round to integer with rounding from FPSCR

Thumb syntax (32-bit, v7)

VRINTR.F32.F32	Sd, Sn
VRINTR.F64.F64	Dd, Dn

VRINTX

Description

Floating-point round to integer with rounding from FPSCR

Thumb syntax (32-bit, v7)

VRINTX.F32.F32	Sd, Sn
VRINTX.F64.F64	Dd, Dn

VRINTZ

Description

Floating-point round to integer towards zero

Thumb syntax (32-bit, v7)

VRINTZ.F32.F32	Sd, Sn
VRINTZ.F64.F64	Dd, Dn

VSELEQ

Description

Floating-point conditional select

Thumb syntax (32-bit, v7)

VSELEQ.F32	Sd, Sn, Sm	[1]
VSELEQ.F64	Dd, Dn, Dm	[1]

Notes

[1] not permitted in an IT block

VSELGE

Description

Floating-point conditional select

Thumb syntax (32-bit, v7)

VSELGE.F32	Sd, Sn, Sm	[1]
VSELGE.F64	Dd, Dn, Dm	[1]

Notes

[1] not permitted in an IT block

VSELGT

Description

Floating-point conditional select

Thumb syntax (32-bit, v7)

VSELGT.F32	Sd, Sn, Sm	[1]
VSELGT.F64	Dd, Dn, Dm	[1]

Notes

[1] not permitted in an IT block

VSQRT

Description

Floating-point square root

Thumb syntax (32-bit, v7)

VSQRT.F32	Sd, Sn
VSQRT.F64	Dd, Dn

VSTR

Description

Floating-point store

Thumb syntax (32-bit, v7)

VSTR.32	Sn, [Rn, #−1020…1020]	[1]
VSTR.64	Dn, [Rn, #−1020…1020]	[1]

Notes

[1] Rn ≠ PC; offset a multiple of 4

VSUB

Description

Floating-point subtract

Thumb syntax (32-bit, v7)

VSUB.F32	Sd, Sn, Sm
VSUB.F64	Dd, Dn, Dm

WFE

Description

Wait for event

Thumb syntax (16-bit, v6K)

WFE

Thumb syntax (32-bit, v7)

WFE

Arm syntax (v)

WFE

WFI

Description

Wait for interrupt

Thumb syntax (16-bit, v6K)

WFI

Thumb syntax (32-bit, v7)

WFI

Arm syntax (v)

WFI

YIELD

Description

Yield

Thumb syntax (16-bit, v6K)

YIELD

Thumb syntax (32-bit, v7)

YIELD

Arm syntax (v)

YIELD

Differences between assemblers

Syntax and Encoding differences

The following sections document the differences in UAL input syntax and the binary encoding of UAL source code. This is particularly important if you expect identical instruction encodings between assemblers, especially when using the SEGGER assembler to assemble existing source code.

MUL and MULS

UAL allows a multiply instruction to be written as MUL Rd, Rn. When the only encoding of this UAL input is a three-operand instructions, MUL Rd, Rn must be interpreted as MUL Rd, Rd, Rn.

The following are the encodings of MUL Rd, Rn and MULS Rd, Rn where only three-operand encoding is possible. The SEGGER assembler follows Arm’s encoding, whereas GNU deviates and IAR rejects correct UAL.

SEGGER	Arm	GNU	IAR
MUL Rd, Rd, Rn	MUL Rd, Rd, Rn	MUL Rd, Rn, Rd	Rejects
MULS Rd, Rd, Rn	MULS Rd, Rd, Rn	MULS Rd, Rn, Rd	Rejects

MULS

UAL allows a multiply instruction to be written as MULS Rd, Rn. The assembler can choose between two-operand form and three-operand form based on the registers Rd and Rn.

The following are the encodings of MULS R1, R2:

SEGGER	Arm	GNU	IAR
MULS.N R1, R2	Rejects	MULS.N R1, R2	MULS.N R1, R2

And MULS R1, R9:

SEGGER	Arm	GNU	IAR
MULS.W R1, R1, R9	MULS.W R1, R1, R9	MULS.W R1, R9, R1	MULS.W R1, R1, R9